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Total properties:
21
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Patent #:
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Issue Dt:
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01/11/1994
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Application #:
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07864701
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Filing Dt:
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04/07/1992
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Title:
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VOLTAGE COMPENSATING CMOS INPUT BUFFER
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Patent #:
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Issue Dt:
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11/02/1993
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Application #:
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07933433
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Filing Dt:
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08/20/1992
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Title:
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METHOD OF FORMING LOCAL ETCH STOP LANDING PADS FOR SIMULTANEOUS, SELF- ALIGNED DRY ETCHING OF CONTACT VIAS WITH VARIOUS DEPTHS
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Patent #:
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Issue Dt:
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06/08/1993
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Application #:
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07946196
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Filing Dt:
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09/16/1992
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Title:
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OUTPUT ESD PROTECTION CIRCUIT
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Patent #:
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Issue Dt:
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01/04/1994
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Application #:
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07981631
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Filing Dt:
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11/25/1992
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Title:
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TRENCH ISOLATION USING GATED SIDEWALLS
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Patent #:
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Issue Dt:
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10/12/1993
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Application #:
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07988626
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Filing Dt:
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12/10/1992
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Title:
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METHOD OF CONDUCTOR ISOLATION FROM A CONDUCTIVE CONTACT PLUG
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Patent #:
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Issue Dt:
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11/01/1994
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Application #:
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08004363
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Filing Dt:
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01/14/1993
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Title:
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ADJUSTABLE BUFFER/DRIVER
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Patent #:
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Issue Dt:
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08/23/1994
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Application #:
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08017067
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Filing Dt:
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02/12/1993
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Title:
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MULTI-PIN STACKED CAPACITOR UTILIZING MICRO VILLUS PATTERNING IN A CONTAINER CELL AND METHOD TO FABRICATE SAME
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Patent #:
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Issue Dt:
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04/19/1994
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Application #:
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08029088
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Filing Dt:
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03/10/1993
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Title:
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ON CHIP DECOUPLING CAPACITOR
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Patent #:
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Issue Dt:
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01/11/1994
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Application #:
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08058554
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Filing Dt:
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05/04/1993
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Title:
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PROCESS TO MANUFACTURE CROWN STACKED CAPACITOR STRUCTURES WITH HSG-RUGGED POLYSILICON ON ALL SIDES OF THE STORAGE NODE
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Patent #:
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Issue Dt:
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08/02/1994
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Application #:
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08104523
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Filing Dt:
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08/10/1993
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Title:
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THIN FILM TRANSISTOR (TFT) LOADS FORMED IN RECESSED PLUGS
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Patent #:
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Issue Dt:
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09/13/1994
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Application #:
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08105276
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Filing Dt:
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08/12/1993
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Title:
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PLANARIZATION OF A GATE ELECTRODE FOR IMPROVED GATE PATTERNING OVER NON-PLANAR ACTIVE AREA ISOLATION
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Patent #:
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Issue Dt:
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08/23/1994
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Application #:
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08106503
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Filing Dt:
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08/13/1993
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Title:
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METHOD FOR FORMING ENHANCED CAPACITANCE STACKED CAPACITOR STRUCTURES USING HEMI-SPHERICAL GRAIN POLYSILICON
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Patent #:
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Issue Dt:
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08/09/1994
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Application #:
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08116100
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Filing Dt:
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09/02/1993
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Title:
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INPUT ESD PROTECTION CIRCUIT
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Patent #:
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Issue Dt:
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10/11/1994
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Application #:
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08122639
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Filing Dt:
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09/15/1993
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Title:
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TECHNIQUE TO FABRICATE A CONTAINER STRUCTURE WITH ROUGH INNER AND OUTER SURFACES
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Patent #:
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Issue Dt:
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11/01/1994
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Application #:
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08135214
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Filing Dt:
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10/12/1993
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Title:
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VOLTAGE COMPENSATING CMOS INPUT BUFFER
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Patent #:
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Issue Dt:
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04/02/1996
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Application #:
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08149855
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Filing Dt:
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11/10/1993
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Title:
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SYSTEM FOR COMPENSATING AGAINST WAFER EDGE HEAT LOSS IN RAPID THERMAL PROCESSING
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Patent #:
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Issue Dt:
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11/08/1994
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Application #:
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08193678
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Filing Dt:
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02/08/1994
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Title:
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BARRIER PROCESS FOR TA2O5 CAPACITOR
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Patent #:
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Issue Dt:
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02/20/1996
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Application #:
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08242230
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Filing Dt:
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05/13/1994
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Title:
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METHOD OF ETCHING WSIX FILMS
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Patent #:
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Issue Dt:
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09/26/1995
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Application #:
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08250897
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Filing Dt:
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05/31/1994
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Title:
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SUB-MICRON DIFFUSION AREA ISOLATION WITH SI-SEG FOR A DRAM ARRAY
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Patent #:
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Issue Dt:
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12/27/1994
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Application #:
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08268489
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Filing Dt:
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06/30/1994
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Title:
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METHOD OF FORMING A LOW RESISTIVE CURRENT PATH BETWEEN A BURIED CONTACT AND A DIFFUSION REGION
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Patent #:
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Issue Dt:
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12/12/1995
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Application #:
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08427941
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Filing Dt:
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04/25/1995
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Title:
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METHOD FOR OPTIMIZING THERMAL BUDGETS IN FABRICATING SEMICONDUCTORS
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