Patent Assignment Details
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| Reel/Frame: | 009369/0355 | |
| Pages: | 3 |
| | Recorded: | 08/07/1998 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/09/2001
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Application #:
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09104921
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Filing Dt:
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06/25/1998
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Title:
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ON CHIP CMOS VLSI REFERENCE VOLTAGE WITH FEEDBACK FOR HYSTERESIS NOISE MARGIN
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Assignee
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| LEGAL DEPARTMENT, M/S 20BN |
| 3000 HANOVER STREET |
| PALO ALTO, CALIFORNIA 94304 |
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Correspondence name and address
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HEWLETT-PACKARD COMPANY
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JEROME DECHANT
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LEGAL DEPARTMENT, IP SECTION
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19111 PRUNERIDGE AVE., M/S 44L18
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CUPERTINO, CA 95014-0795
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