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Patent #:
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Issue Dt:
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11/07/1978
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Application #:
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05799509
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Filing Dt:
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05/23/1977
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Title:
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PROGRAMMABLE ARRAY LOGIC CIRCUIT
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Patent #:
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Issue Dt:
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01/05/1988
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Application #:
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06433253
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Filing Dt:
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10/07/1982
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Title:
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APPARATUS FOR PRODUCING ANY ONE OF A PLURALITY OF SIGNALS AT A SINGLE OUTPUT
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Patent #:
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Issue Dt:
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09/02/1986
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Application #:
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06562506
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Filing Dt:
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12/15/1983
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Title:
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HIGH CONDUCTANCE CIRCUIT FOR PROGRAMMABLE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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11/19/1985
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Application #:
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06575845
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Filing Dt:
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01/30/1984
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Title:
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PROGRAMMABLE ARRAY LOGIC CIRCUIT WITH SHARED PRODUCT TERMS
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Patent #:
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Issue Dt:
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11/25/1986
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Application #:
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06621536
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Filing Dt:
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06/18/1984
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Title:
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PROGRAMMABLE ARRAY LOGIC CIRCUIT WITH TESTING AND VERIFICATION CIRCUITRY
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Patent #:
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Issue Dt:
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01/20/1987
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Application #:
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06626377
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Filing Dt:
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06/29/1984
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Title:
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FAST AND GATE WITH PROGRAMMABLE OUTPUT POLARITY
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Patent #:
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Issue Dt:
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02/24/1987
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Application #:
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06627401
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Filing Dt:
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07/03/1984
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Title:
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CURRENT SOURCE WHICH SAVES POWER IN PROGRAMMABLE LOGIC ARRAY CIRCUITRY
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Patent #:
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Issue Dt:
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06/02/1987
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Application #:
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06635861
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Filing Dt:
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07/30/1984
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Title:
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SHORT DETECTOR FOR FUSIBLE LINK ARRAY USING A PAIR OF PARALLEL CONNECTED REFERENCE
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Patent #:
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Issue Dt:
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11/25/1986
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Application #:
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06663806
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Filing Dt:
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10/22/1984
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Title:
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FUSIBLE LINK SHORT DETECTOR WITH ARRAY OF REFERENCE FUSES
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Patent #:
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Issue Dt:
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06/02/1987
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Application #:
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06682381
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Filing Dt:
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12/17/1984
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Title:
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PROGRAMMABLE OUTPUT POLARITY DEVICE
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Patent #:
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Issue Dt:
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03/21/1989
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Application #:
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06715141
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Filing Dt:
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03/22/1985
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Title:
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PROGRAMMABLE LOGIC ARRAY USING EMITTER-COUPLED LOGIC
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Patent #:
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Issue Dt:
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08/04/1987
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Application #:
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06715214
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Filing Dt:
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03/22/1985
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Title:
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OUTPUT CIRCUIT FOR A PROGRAMMABLE LOGIC ARRAY
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Patent #:
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Issue Dt:
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05/03/1988
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Application #:
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06717640
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Filing Dt:
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03/29/1985
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Title:
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MULTIPLE ARRAY CUSTOMIZABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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01/20/1987
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Application #:
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06741658
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Filing Dt:
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06/05/1985
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Title:
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SHORT DETECTOR FOR FUSIBLE LINK ARRAY USING SINGLE REFERENCE FUSE
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Patent #:
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Issue Dt:
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07/19/1988
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Application #:
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06765038
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Filing Dt:
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08/12/1985
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Title:
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PROGRAMMABLE LOGIC ARRAY WITH ADDED ARRAY OF GATES AND ADDED OUTPUT ROUTING FLEXIBILITY
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Patent #:
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Issue Dt:
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07/14/1987
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Application #:
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06794216
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Filing Dt:
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10/31/1985
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Title:
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METHOD OF MAKING IMPROVED METAL SILICIDE FUSE FOR INTEGRATED CIRCUIT STRUCTURE
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Patent #:
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Issue Dt:
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09/13/1988
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Application #:
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06795159
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Filing Dt:
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11/05/1985
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Title:
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PROGRAMMABLE LOGIC CELL WITH FLEXIBLE CLOCKING AND FLEXIBLE FEEDBACK
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Patent #:
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Issue Dt:
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10/24/1989
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Application #:
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06827840
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Filing Dt:
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02/07/1986
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Title:
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LOGIC CONTROLLER HAVING PROGRAMMABLE LOGIC"AND" ARRAY USING A PROGRAMMABLE GRAY-CODE COUNTER
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Patent #:
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Issue Dt:
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01/03/1989
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Application #:
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06852473
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Filing Dt:
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04/15/1986
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Title:
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FUSIBLE LINK STRUCTURE FOR INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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12/06/1988
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Application #:
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06864185
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Filing Dt:
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05/16/1986
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Title:
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PROGRAMMABLE ARRAY LOGIC CELL
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Patent #:
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Issue Dt:
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07/19/1988
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Application #:
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06868970
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Filing Dt:
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05/30/1986
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH BURIED REGISTERS SELECTIVELY MULTIPLEXED WITH OUTPUT REGISTERS TO PORTS , AND PRELOAD CIRCUITRY THEREFOR
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Patent #:
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Issue Dt:
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04/26/1988
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Application #:
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06888559
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Filing Dt:
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07/22/1986
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Title:
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METHOD FOR FORMING A FUSE
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Patent #:
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Issue Dt:
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10/18/1988
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Application #:
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06891514
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Filing Dt:
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07/29/1986
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Title:
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MONOSTABLE LOGIC GATE IN A PROGRAMMABLE LOGIC ARRAY
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Patent #:
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Issue Dt:
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07/18/1989
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Application #:
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07047794
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Filing Dt:
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05/06/1987
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Title:
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BIPOLAR PROGRAMMABEL LOGIC ARRAY
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Patent #:
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Issue Dt:
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12/06/1988
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Application #:
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07066915
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Filing Dt:
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06/25/1987
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Title:
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TEMPERATURE-COMPENSATED INTERFACE CIRCUIT "OR-TIED" CONNECTION OF A PLA DEVICE AND A TTL OUTPUT BUFFER
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Patent #:
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Issue Dt:
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09/05/1989
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Application #:
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07141239
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Filing Dt:
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01/05/1988
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Title:
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ECL PROGRAMMABLE LOGIC ARRAY WITH DIRECT TESTING MEANS FOR VERIFICATION OF PROGRAMMED STATE
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Patent #:
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Issue Dt:
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06/05/1990
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Application #:
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07178707
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Filing Dt:
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04/07/1988
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Title:
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MULTIPLE ARRAY CUSTOMIZABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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09/20/1994
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Application #:
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07207317
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Filing Dt:
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06/15/1988
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Title:
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PROGRAMMABLE SYSTEM SYNCHRONIZER
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Patent #:
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Issue Dt:
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04/02/1991
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Application #:
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07207323
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Filing Dt:
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06/15/1988
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Title:
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OPTIMIZED ELECTRICALLY ERASABLE PLA CELL FOR MINIMUM READ DISTURB
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Patent #:
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Issue Dt:
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07/03/1990
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Application #:
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07217942
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Filing Dt:
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07/12/1988
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH OBSERVABILITY AND PRELOAD CIRCUITRY FOR BURIED STATE REGISTERS
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Patent #:
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Issue Dt:
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10/16/1990
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Application #:
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07243574
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Filing Dt:
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09/12/1988
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Title:
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FLEXIBLE, PROGRAMMABLE CELL ARRAY INTERCONNECTED BY A PROGRAMMABLE SWITCH MATRIX
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Patent #:
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Issue Dt:
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05/08/1990
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Application #:
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07274633
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Filing Dt:
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11/15/1988
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Title:
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EEPROM USING A MERGED SOURCE AND CONTROL GATE
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Patent #:
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Issue Dt:
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04/03/1990
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Application #:
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07285721
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Filing Dt:
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12/16/1988
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Title:
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POLARITY OPTION CONTROL LOGIC FOR USE WITH A REGISTER OF A PROGRAMMABLE LOGIC ARRAY MACROCELL
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Patent #:
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Issue Dt:
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08/07/1990
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Application #:
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07325402
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Filing Dt:
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03/17/1989
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Title:
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HIGH SPEED COMPLIMENTARY OUTPUT STAGE UTILIZING CURRENT STEERING TRANSISTORS AND A SINGLE CURRENT SOURCE
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Patent #:
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Issue Dt:
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06/12/1990
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Application #:
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07336628
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Filing Dt:
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04/10/1989
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Title:
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OUTPUT CIRCUIT FOR A PROGRAMMABLE LOGIC ARRAY
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Patent #:
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Issue Dt:
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06/19/1990
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Application #:
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07351011
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Filing Dt:
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06/16/1989
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Title:
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OPTIMIZED E2 PAL CELL FOR MINIMUM READ DISTURB
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Patent #:
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Issue Dt:
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01/12/1993
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Application #:
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07370148
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Filing Dt:
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06/21/1989
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Title:
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PROGRAMMABLE EXPANDABLE CONTROLLER WITH FLEXIBLE I/O
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Patent #:
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Issue Dt:
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05/18/1993
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Application #:
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07394221
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Filing Dt:
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08/15/1989
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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06/25/1991
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Application #:
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07401528
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Filing Dt:
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08/30/1989
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Title:
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PROGRAMMABLE LOGIC ARRAY USING INTERNALLY GENERATED DYNAMIC LOGIC SIGNALS AS SELECTION SIGNALS FOR CONTROLLING ITS FUNCTIONS
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Patent #:
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Issue Dt:
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05/21/1991
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Application #:
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07425306
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Filing Dt:
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10/23/1989
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Title:
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METHOD AND APPARATUS FOR PROGRAM VERIFICATION OF A FIELD PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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08/03/1993
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Application #:
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07429125
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Filing Dt:
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10/30/1989
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/ OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
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Patent #:
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Issue Dt:
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11/09/1993
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Application #:
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07442528
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Filing Dt:
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11/27/1989
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED CONFIGURABLE LOGIC BLOCK
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Patent #:
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Issue Dt:
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08/20/1991
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Application #:
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07464560
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Filing Dt:
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01/16/1990
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH SUBROUTINE STACK AND RANDOM ACCESS MEMORY
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Patent #:
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Issue Dt:
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05/14/1991
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Application #:
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07490808
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Filing Dt:
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03/07/1990
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Title:
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MULTIPLE ARRAY HIGH PERFORMANCE PROGRAMMABLE LOGIC DEVICE FAMILY
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Patent #:
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Issue Dt:
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07/07/1992
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Application #:
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07490817
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Filing Dt:
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03/07/1990
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Title:
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APPARATUS AND METHOD FOR ALLOCATION OF RESOURCES IN PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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02/09/1993
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Application #:
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07503049
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Filing Dt:
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04/02/1990
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Title:
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PROGRAMMABNLE GATE ARRAY WITH LOGIC CELLS HAVING CONFIGURABLE OUTPUT ENABLE
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Patent #:
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Issue Dt:
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07/27/1993
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Application #:
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07514297
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Filing Dt:
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04/25/1990
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Title:
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PROGRAMMABLE GATE ARRAY WITH LOGIC CELLS HAVING SYMMETRICAL INPUT/OUTPUT STRUCTURES
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Patent #:
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Issue Dt:
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10/19/1993
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Application #:
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07538211
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Filing Dt:
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06/14/1990
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Title:
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INTERCONNECT STRUCTURE FOR PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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01/07/1992
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Application #:
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07582013
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Filing Dt:
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09/13/1990
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Title:
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SELF-LATCHING LOGIC GATE FOR USE IN PROGRAMMABLE LOGIC ARRAY CIRCUITS
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Patent #:
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Issue Dt:
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12/01/1992
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Application #:
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07603817
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Filing Dt:
|
10/25/1990
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH OBSERVABILITY AND PRELOADABILITY FOR BURIED STATE REGISTERS
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Patent #:
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|
Issue Dt:
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03/31/1992
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Application #:
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07604824
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Filing Dt:
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10/26/1990
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Title:
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OPTIMIZED ELECTRICALLY ERASABLE CELL FOR MINIMUM READ DISTURB AND ASSOCIATED METHOD OF SENSING
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Patent #:
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Issue Dt:
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07/06/1993
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Application #:
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07699427
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Filing Dt:
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05/13/1991
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Title:
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FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
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Patent #:
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Issue Dt:
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03/02/1993
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Application #:
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07701790
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Filing Dt:
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05/17/1991
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Title:
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PROGRAMMABLE LOGIC DEVICE INCORPORATING DIGITAL-TO-ANALOG CONVERTER
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Patent #:
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Issue Dt:
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10/06/1992
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Application #:
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07703455
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Filing Dt:
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05/21/1991
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Title:
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PROGRAMMABLE LOGIC DEVICE INCORPORATING VOLTAGE COMPARATOR
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Patent #:
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Issue Dt:
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09/21/1993
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Application #:
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07736205
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Filing Dt:
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07/26/1991
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Title:
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PLDS WITH HIGH DRIVE CAPABILITY
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Patent #:
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Issue Dt:
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09/29/1992
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Application #:
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07779547
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Filing Dt:
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10/18/1991
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH MULTIPLE, FLEXIBLE ASYNCHRONOUS PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED SWITCH MATRIX
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Patent #:
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Issue Dt:
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07/25/1995
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Application #:
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07816515
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Filing Dt:
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12/31/1991
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Title:
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A HIGH SPEED CENTRALIZED SWITCH MATRIX FOR A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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11/09/1993
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Application #:
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07891603
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Filing Dt:
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06/01/1992
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Title:
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PROGRAMMABLE, EXPANDABLE CONTROLLER WITH FLEXIBLE I/O
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Patent #:
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Issue Dt:
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08/24/1993
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Application #:
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07897575
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Filing Dt:
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06/11/1992
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Title:
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PRECISION TIMING CONTROL PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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02/06/1996
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Application #:
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07924201
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Filing Dt:
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08/03/1992
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Title:
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FLEXIBLE SYNCHRONOUS/ASYNCHRONOUS CELL STRUCTURE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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10/10/1995
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Application #:
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07924685
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Filing Dt:
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08/03/1992
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Title:
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ARCHITECTURE OF A MULTIPLE ARRAY HIGH DENSITY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES
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Patent #:
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Issue Dt:
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05/24/1994
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Application #:
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07930969
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Filing Dt:
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08/13/1992
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Title:
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PROGRAMMABLE OUTPUT SLEW RATE CONTROL
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Patent #:
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Issue Dt:
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11/23/1993
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Application #:
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08002693
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Filing Dt:
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01/11/1993
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Title:
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PROGRAMMABLE VOLTAGE HYSTERESIS ON A VOLTAGE COMPARATOR
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Patent #:
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Issue Dt:
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07/12/1994
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Application #:
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08012573
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Filing Dt:
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02/01/1993
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/ OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
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Patent #:
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Issue Dt:
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04/18/1995
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Application #:
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08017084
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Filing Dt:
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02/12/1993
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Title:
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LOW POWER CONSUMPTION AND HIGH SPEED NOR GATE INTEGRATED CIRCUIT
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Patent #:
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Issue Dt:
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04/26/1994
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Application #:
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08024521
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Filing Dt:
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03/01/1993
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Title:
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SWITCH MATRIX MULTIPLEXERS
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Patent #:
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Issue Dt:
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10/25/1994
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Application #:
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08025551
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Filing Dt:
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03/03/1993
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Title:
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PROGRAMMABLE GATE ARRAY WITH IMPROVED INTERCONNECT STRUCTURE, INPUT/OUTPUT STRUCTURE AND CONFIGURABLE LOGIC BLOCK
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Patent #:
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Issue Dt:
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04/11/1995
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Application #:
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08034510
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Filing Dt:
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03/19/1993
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Title:
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INPUT BUFFER UTILIZING A CASCODE TO PROVIDE A ZERO POWER TTL TO CMOS INPUT WITH HIGH SPEED SWITCHING
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Patent #:
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Issue Dt:
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11/21/1995
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Application #:
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08034537
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Filing Dt:
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03/19/1993
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Title:
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CASCADE ARRAY CELL PARTITIONING FOR A SENSE AMPLIFIER OF A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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07/01/1997
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Application #:
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08080658
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Filing Dt:
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06/18/1993
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Title:
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PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES
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Patent #:
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Issue Dt:
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06/20/1995
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Application #:
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08085601
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Filing Dt:
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06/30/1993
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Title:
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PINOUT ARCHITECTURE FOR A FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
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Patent #:
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Issue Dt:
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07/25/1995
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Application #:
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08118123
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Filing Dt:
|
09/07/1993
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Title:
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INPUT TRANSITION DETECTION CIRCUIT FOR ZERO-POWER PART
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Patent #:
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Issue Dt:
|
04/25/1995
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Application #:
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08118432
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Filing Dt:
|
09/08/1993
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Title:
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LATCHING ZERO-POWER SENSE AMPLIFIER WITH CASCODE
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Patent #:
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Issue Dt:
|
10/10/1995
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Application #:
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08118801
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Filing Dt:
|
09/08/1993
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Title:
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ZERO-POWER OR GATE
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Patent #:
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Issue Dt:
|
08/01/1995
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Application #:
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08128628
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Filing Dt:
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09/28/1993
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Title:
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HIGH SPEED CMOS OUTPUT BUFFER CIRCUIT MINIMIZES PROPAGATION DELAY AND CROWBAR CURRENT
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Patent #:
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Issue Dt:
|
05/23/1995
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Application #:
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08134523
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Filing Dt:
|
10/08/1993
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Title:
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INPUT LEVEL DETECTION CIRCUIT
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Patent #:
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Issue Dt:
|
03/28/1995
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Application #:
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08135812
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Filing Dt:
|
10/12/1993
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Title:
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INPUT BUFFER CIRCUIT WITH IMPROVED SPEED PERFORMANCE
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Patent #:
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|
Issue Dt:
|
08/15/1995
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Application #:
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08137437
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Filing Dt:
|
10/15/1993
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Title:
|
CMOS LOGIC GATE CLAMPING CIRCUIT
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Patent #:
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|
Issue Dt:
|
07/11/1995
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Application #:
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08138303
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Filing Dt:
|
10/15/1993
|
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Title:
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HIGH SPEED NOR GATE WITH SMALL OUTPUT VOLTAGE SWINGS
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|
|
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Patent #:
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|
Issue Dt:
|
05/23/1995
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Application #:
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08138532
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Filing Dt:
|
10/15/1993
|
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Title:
|
HIGH-SPEED SENSE AMPLIFIER WITH REGULATED FEEDBACK
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|
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Patent #:
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|
Issue Dt:
|
09/20/1994
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Application #:
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08149029
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Filing Dt:
|
11/08/1993
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Title:
|
INTEGRATED CIRCUIT PROGRAMMABLE SEQUENCING ELEMENT APPARATUS
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Patent #:
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|
Issue Dt:
|
06/06/1995
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Application #:
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08271872
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Filing Dt:
|
07/07/1994
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Title:
|
PROGRAMMABLE GATE ARRAY DEVICE HAVING CASCADED MEANS FOR FUNCTION DEFINITION
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Patent #:
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|
Issue Dt:
|
10/22/1996
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Application #:
|
08341432
|
Filing Dt:
|
11/17/1994
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|
Title:
|
SENSE AMPLIFIER AND OR GATE FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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|
|
|
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Patent #:
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|
Issue Dt:
|
02/27/1996
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Application #:
|
08341499
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Filing Dt:
|
11/17/1994
|
|
Title:
|
OUTPUT BUFFER FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
09/16/1997
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Application #:
|
08341636
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Filing Dt:
|
11/17/1994
|
|
Title:
|
INPUT BUFFER FOR A HIGH DENSITY PROGRAMMABLE LOGIC DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
01/16/1996
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Application #:
|
08375465
|
Filing Dt:
|
01/18/1995
|
|
Title:
|
FAMILY OF MULTIPLE SEGMENTED PROGRAMMABLE LOGIC BLOCKS INTERCONNECTED BY A HIGH SPEED CENTRALIZED SWITCH MATRIX
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|
|
|
|
Patent #:
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|
Issue Dt:
|
02/06/1996
|
Application #:
|
08423303
|
Filing Dt:
|
04/18/1995
|
|
Title:
|
CONSTANT DELAY INTERCONNECT FOR COUPLING CONFIGURABLE LOGIC BLOCKS
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|
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|
Patent #:
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|
Issue Dt:
|
01/21/1997
|
Application #:
|
08427117
|
Filing Dt:
|
04/21/1995
|
|
Title:
|
CMOS MEMORY CELL WITH GATE OXIDE OF BOTH NMOS AND PMOS TRANSISTORS AS TUNNELING WINDOW FOR PROGRAM AND ERASE
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|
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|
Patent #:
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|
Issue Dt:
|
02/13/1996
|
Application #:
|
08444306
|
Filing Dt:
|
05/18/1995
|
|
Title:
|
CASCODE ARRAY CELL PARTITIONING FOR A SENSE AMPLIFIER OF A PROGRAMMABLE LOGIC DEVICE
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|
Patent #:
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|
Issue Dt:
|
01/14/1997
|
Application #:
|
08447991
|
Filing Dt:
|
05/23/1995
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|
Title:
|
COMPLETELY COMPLEMENTARY MOS MEMORY CELL WITH TUNNELING THROUGH THE NMOS AND PMOS TRANSISTORS DURING PROGRAM AND ERASE
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|
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|
Patent #:
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|
Issue Dt:
|
05/26/1998
|
Application #:
|
08449384
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Filing Dt:
|
05/23/1995
|
|
Title:
|
METHOD OF MAKING A SPACER BASED ANTIFUSE STRUCTURE FOR LOW CAPACITANCE AND HIGH RELIABILITY
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|
Patent #:
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|
Issue Dt:
|
04/15/1997
|
Application #:
|
08456946
|
Filing Dt:
|
06/01/1995
|
|
Title:
|
PROGRAMMABLE LOGIC DEVICE WITH INTERNAL TIME-CONSTANT MULTIPLEXING OF SIGNALS FROM EXTERNAL INTERCONNECT BUSES
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|
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|
Patent #:
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|
Issue Dt:
|
12/31/1996
|
Application #:
|
08458865
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
MACROCELL AND CLOCK SIGNAL ALLOCATION CIRCUIT FOR A PROGRAMMABLE LOGIC DEVICE (PLD) ENABLING PLD RESOURCES TO PROVIDE MULTIPLE FUNCTIONS
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|
Patent #:
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|
Issue Dt:
|
10/06/1998
|
Application #:
|
08459230
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Filing Dt:
|
06/02/1995
|
|
Title:
|
MULTI-TIERED HIERARCHICAL HIGH SPEED SWITCH MATRIX STRUCTURE FOR VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES
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|
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|
Patent #:
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|
Issue Dt:
|
07/14/1998
|
Application #:
|
08459234
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Filing Dt:
|
06/02/1995
|
|
Title:
|
PROGRAMMABLE UNIFORM SYMMETRICAL DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/2003
|
Application #:
|
08459570
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
PROGRAMMABLE OPTIMIZED-DISTRIBUTION LOGIC ALLOCATOR FOR A HIGH-DENSITY COMPLEX PLD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/10/1997
|
Application #:
|
08459786
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
P-TYPE FLIP-FLOP
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/28/1996
|
Application #:
|
08459960
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Filing Dt:
|
06/02/1995
|
|
Title:
|
VERY HIGH-DENSITY COMPLEX PROGRAMMABLE LOGIC DEVICES WITH A MULTI-TIERED HIERARCHICAL SWITCH MATRIX AND OPTIMIZED FLIXIBLE LOGIC ALLOCATION
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|
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|
Patent #:
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|
Issue Dt:
|
12/17/1996
|
Application #:
|
08461196
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Filing Dt:
|
06/05/1995
|
|
Title:
|
ARRAY OF CONFIGURABLE LOGIC BLOCKS INCLUDING CASCADABLE LOOKUP TABLES
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|
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|
|
Patent #:
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|
Issue Dt:
|
11/21/1995
|
Application #:
|
08462934
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Filing Dt:
|
06/05/1995
|
|
Title:
|
ARRAY OF CONFIGURABLE LOGIC BLOCKS EACH INCLUDING A FIRST LOOKUP TABLE OUTPUT COUPLED TO SELECTIVELY REPLACE AN OUTPUT OF SECOND LOOKUP WITH AN ALTERNATE FUNCTION OUTPUT
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|
