Patent Assignment Details
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| Reel/Frame: | 009649/0771 | |
| Pages: | 2 |
| | Recorded: | 12/04/1998 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09135892
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Filing Dt:
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08/18/1998
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN AND EVALUATION SYSTEM USING CYCLE BASE TIMING
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Assignee
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| SHINJUKU-KU |
| NS BUILDING, 4-1 NISHI-SHINJUKU 2-CHOME |
| TOKYO, JAPAN |
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Correspondence name and address
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MURAMATSU & ASSOCIATES
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YASUO MURAMATSU
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SECOND FLOOR
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7700 IRVINE CENTER DRIVE, SUITE 225
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IRVINE, CA 92618
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