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Total properties:
56
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Patent #:
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|
Issue Dt:
|
08/28/1990
|
Application #:
|
06827269
|
Filing Dt:
|
02/06/1986
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|
Title:
|
CUP CHIP HAVING CACHE TAG COMPARATOR AND ADDRESS TRANSLATION UNIT ON CHIP AND CONNECTED TO OFF-CHIP CACHE AND MAIN MEMORIES
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Patent #:
|
|
Issue Dt:
|
02/14/1989
|
Application #:
|
06860304
|
Filing Dt:
|
05/05/1986
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|
Title:
|
WRITE BUFFER
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/1989
|
Application #:
|
06945486
|
Filing Dt:
|
12/23/1986
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|
Title:
|
RISC COMPUTER WITH UNALIGNED REFERENCE HANDLING AND METHOD FOR THE SAME
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|
|
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Patent #:
|
|
Issue Dt:
|
11/07/1989
|
Application #:
|
07161543
|
Filing Dt:
|
02/29/1988
|
|
Title:
|
METHOD AND APPARATUS FOR PRECISE FLOATING POINT EXCEPTIONS
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|
|
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Patent #:
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|
Issue Dt:
|
06/25/1991
|
Application #:
|
07255791
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Filing Dt:
|
10/11/1988
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|
Title:
|
PROCESSOR CONTROLLED INTERFACE WITH INSTRUCTION STREAMING
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|
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Patent #:
|
|
Issue Dt:
|
09/25/1990
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Application #:
|
07277406
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Filing Dt:
|
11/28/1988
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|
Title:
|
DUAL BYTE ORDER COMPUTER ARCHITECTURE A FUNCTIONAL UNIT FOR HANDLING DATA SETS WITH DIFFERENT BYTE ORDERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/17/1993
|
Application #:
|
07366344
|
Filing Dt:
|
06/14/1989
|
|
Title:
|
TRANSLATION LOOKASIDE BUFFER SHUTDOWN SCHEME
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1993
|
Application #:
|
07444594
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
TWO-LEVEL TRANSLATION LOOK-ASIDE BUFFER USING PARTIAL ADDRESSES FOR ENHANCED SPEED
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1993
|
Application #:
|
07444633
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
SLOT DETERMINATION MECHANISM USING PULSE COUNTING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1992
|
Application #:
|
07444639
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
INTERRUPT REPORTING FOR SINGLE-BIT MEMORY ERRORS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/1991
|
Application #:
|
07448715
|
Filing Dt:
|
12/11/1989
|
|
Title:
|
DIFFERENTIAL BUS WITH SPECIFIED DEFAULT VALUE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/1992
|
Application #:
|
07491114
|
Filing Dt:
|
03/09/1990
|
|
Title:
|
SYSTEM HAVING AN ADDRESS GENERATING UNIT AND A TAG COMPARATOR PACKAGED AS AN INTEGRATED CIRCUIT SEPERATE FROM CACHE TAG MEMORY AND CACHE DATA MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/1994
|
Application #:
|
07573926
|
Filing Dt:
|
08/28/1990
|
|
Title:
|
LOW-NOISE HIGH-SPEED OUTPUT BUFFER AND METH0D FOR CONTROLLING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1993
|
Application #:
|
07644705
|
Filing Dt:
|
01/23/1991
|
|
Title:
|
VARIABLE PAGE SIZE PER ENTRY TRANSLATION LOOK-ASIDE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/1992
|
Application #:
|
07659526
|
Filing Dt:
|
02/22/1991
|
|
Title:
|
VARIABLE DELAY LINE PHASE-LOCKED LOOP CIRCUIT SYNCHRONIZATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/1994
|
Application #:
|
07892918
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
SENSE AMP FOR BIT LINE SENSING AND DATA LATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/1994
|
Application #:
|
07892919
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
REDUNDANCY SELECTION APPARATUS AND METHOD FOR AN ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/1994
|
Application #:
|
07893156
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
REDUNDANT ELEMENT SUBSTITUTION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/18/1995
|
Application #:
|
07901910
|
Filing Dt:
|
06/19/1992
|
|
Title:
|
SYSTEM AND METHOD FOR BOOTING COMPUTER FOR OPERATION IN EITHER OF TWO BYTE-ORDER MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/13/1996
|
Application #:
|
07918819
|
Filing Dt:
|
07/22/1992
|
|
Title:
|
APPARATUS FOR DETECTING ANY SINGLE BIT ERROR, DETECTING ANY TWO BIT ERROR, AND DETECTING ANY THREE OR FOUR BIT ERROR IN A GROUP OF FOUR BITS FOR A 25- OR 64- BIT DATA WORD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/31/1994
|
Application #:
|
07933467
|
Filing Dt:
|
08/21/1992
|
|
Title:
|
CLOCK DISTRIBUTION SYSTEM FOR AN INTEGRATED CIRCUIT DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/12/1996
|
Application #:
|
07951471
|
Filing Dt:
|
09/25/1992
|
|
Title:
|
TLB WITH TWO PHYSICAL PAGES PER VIRTUAL TAG
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/03/1994
|
Application #:
|
07956867
|
Filing Dt:
|
10/01/1992
|
|
Title:
|
BINARY SHIFTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/28/1994
|
Application #:
|
08019541
|
Filing Dt:
|
02/18/1993
|
|
Title:
|
TRANSLATION LOOKASIDE BUFFER SHUTDOWN SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/1994
|
Application #:
|
08059715
|
Filing Dt:
|
05/10/1993
|
|
Title:
|
CACHE MEMORY SYSTEM EMPLOYING VIRTUAL ADDRESS PRIMARY INSTRUCTION AND DATA CACHES AND PHYSICAL ADDRESS SECONDARY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/12/1995
|
Application #:
|
08063183
|
Filing Dt:
|
05/17/1993
|
|
Title:
|
UNIFIED FLOATING POINT AND INTEGER DATAPATH FOR A RISC PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/14/1995
|
Application #:
|
08127105
|
Filing Dt:
|
09/27/1993
|
|
Title:
|
SYSTEM FOR OBTAINING CORRECT BYTE ADDRESSES BY XOR-ING 2 LSB BITS OF BYTE ADDRESS WITH BINARY 3 TO FACILITATE COMPATIBILITY BETWEEN COMPUTER ARCHITECTURE HAVING DIFFERENT MEMORY ORDERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/1996
|
Application #:
|
08168822
|
Filing Dt:
|
12/15/1993
|
|
Title:
|
VARIABLE PAGE SIZE TRANSLATION LOOKASIDE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/23/1996
|
Application #:
|
08168832
|
Filing Dt:
|
12/15/1993
|
|
Title:
|
MEMORY SYSTEM INCLUDING LOCAL AND GLOBAL CACHES FOR STORING FLOATING POINT AND INTEGER DATA
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/30/1996
|
Application #:
|
08172684
|
Filing Dt:
|
12/22/1993
|
|
Title:
|
CACHE MEMORY SYSTEM EMPLOYING VIRTUAL ADDRESS PRIMARY INSTRUCTION AND DATA CACHES AND PHYSICAL ADDRESS SECONDARY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/1995
|
Application #:
|
08212377
|
Filing Dt:
|
03/11/1994
|
|
Title:
|
HYBRID CACHE HAVING PHYSICAL-CACHE AND VIRTUAL-CACHE CHARACTERISTICS AND METHOD FOR ACCESSING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/1995
|
Application #:
|
08223388
|
Filing Dt:
|
04/05/1994
|
|
Title:
|
BACKWARD-COMPATIBLE COMPUTER ARCHITECTURE WITH EXTENDED WORD SIZE AND ADDRESS SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/02/1996
|
Application #:
|
08245200
|
Filing Dt:
|
05/17/1994
|
|
Title:
|
COMPACT DUAL FUNCTION ADDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/08/1997
|
Application #:
|
08245983
|
Filing Dt:
|
05/17/1994
|
|
Title:
|
PRECISE TRANSLATION LOOKASIDE BUFFER ERROR DETECTION AND SHUTDOWN CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/1996
|
Application #:
|
08324861
|
Filing Dt:
|
10/18/1994
|
|
Title:
|
RESCHEDULING CONFLICTING ISSUED INSTRUCTIONS BY DELAYING ONE CONFLICTING INSTRUCTION INTO THE SAME PIPELINE STAGE AS A THIRD NON-CONFLICTING INSTRUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/1996
|
Application #:
|
08378844
|
Filing Dt:
|
01/26/1995
|
|
Title:
|
SYSTEM FOR BOOTING COMPUTER FOR OPERATION IN EITHER ONE OF TWO BYTE-ORDER MODES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/1996
|
Application #:
|
08379710
|
Filing Dt:
|
01/27/1995
|
|
Title:
|
SYSTEM AND METHOD FOR OBTAINING CORRECT BYTE ADDRESSES BY USING LOGICAL OPERATIONS ON 2 LEAST SIGNIFICANT BITS OF BYTE ADDRESS TO FACILITATE COMPATIBILITY BETWEEN COMPUTER ARCHITECTURES HAVING DIFFERENT MEMORY ORDERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08391946
|
Filing Dt:
|
02/21/1995
|
|
Title:
|
BACKWARD-COMPATIBLE COMPUTER ARCHITECTURE WITH EXTENDED WORD SIZE AND ADDRESS SPACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
08404625
|
Filing Dt:
|
03/14/1995
|
|
Title:
|
ADDRESS QUEUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/09/1997
|
Application #:
|
08405622
|
Filing Dt:
|
03/15/1995
|
|
Title:
|
METHOD AND APPARATUS FOR REDUCING DELAYS FOLLOWING THE EXECUTION OF A BRANCH INSTRUCTION PIPELINE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/24/1998
|
Application #:
|
08410524
|
Filing Dt:
|
03/24/1995
|
|
Title:
|
CONSISTENTLY SPECIFYING WAY DESTINATIONS THROUGH PREFETCHING HINTS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/31/1996
|
Application #:
|
08449588
|
Filing Dt:
|
05/24/1995
|
|
Title:
|
METHOD AND APPARATUS FOR RESTARTING PIPELINE PROCESSING
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08484313
|
Filing Dt:
|
06/07/1995
|
|
Title:
|
SOFTWARE INVALIDATION IN A MULTIPLE LEVEL MULTIPLE CACHE SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/14/1998
|
Application #:
|
08487240
|
Filing Dt:
|
06/13/1995
|
|
Title:
|
CONFLICT RESOLUTION IN INTERLEAVED MEMORY SYSTEMS WITH MULTIPLE PARALLEL ACCESSES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/22/1996
|
Application #:
|
08491491
|
Filing Dt:
|
06/16/1995
|
|
Title:
|
RISC PROCESSOR HAVING IMPROVED INSTRUCTION FETCHING CAPABILITY AND UTILIZING ADDRESS BIT PREDECODING FOR A SEGMENTED CACHE MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/23/1997
|
Application #:
|
08561914
|
Filing Dt:
|
11/22/1995
|
|
Title:
|
LOW-POWER, COMPACT DIGITAL LOGIC TOPOLOGY THAT FACILITATES LARGE FAN-IN AND HIGH-SPEED CIRCUIT PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/09/1999
|
Application #:
|
08686363
|
Filing Dt:
|
07/24/1996
|
|
Title:
|
SYSTEM AND METHOD FOR FETCHING MULTIPLE GROUPS OF INSTRUCTIONS FROM AN INTSTRUCTION CACHE IN A RISC PROCESSOR SYSTEM FOR EXECUTION DURING SEPARATE CYCLES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/1998
|
Application #:
|
08715246
|
Filing Dt:
|
09/19/1996
|
|
Title:
|
PROCESSOR CHIP HAVING ON-CHIP CIRCUITRY FOR GENERATING A PROGRAMMABLE EXTERNAL CLOCK SIGNAL AND FOR CONTROLLING DATA PATTERNS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/24/2001
|
Application #:
|
08772233
|
Filing Dt:
|
12/23/1996
|
|
Title:
|
TRANSLATION LOOKASIDE BUFFER WITH VIRTUAL ADDRESS CONFLICT PREVENTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/1998
|
Application #:
|
08796142
|
Filing Dt:
|
02/07/1997
|
|
Title:
|
PIPELINE PROCESSOR WITH ENHANCED METHOD AND APPARATUS FOR RESTORING REGISTER-RENAMING INFORMATION IN THE EVENT OF A BRANCH MISPREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/15/2003
|
Application #:
|
08813500
|
Filing Dt:
|
03/07/1997
|
|
Title:
|
CACHE MEMORY WITH DUAL-WAY ARRAYS AND MULTIPLEXED PARALLEL OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
08935369
|
Filing Dt:
|
09/22/1997
|
|
Title:
|
INSTRUCTION PREDICTION BASED ON FILTERING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/26/1999
|
Application #:
|
08947648
|
Filing Dt:
|
10/09/1997
|
|
Title:
|
METHOD FOR PROVIDING EXTENDED PRECISION IN SIMD VECTOR ARITHMETIC OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/03/1999
|
Application #:
|
08947649
|
Filing Dt:
|
10/09/1997
|
|
Title:
|
ALIGNMENT AND ORDERING OF VECTOR ELEMENTS FOR SINGLE INSTRUCTION MULTIPLE DATA PROCESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/29/2001
|
Application #:
|
08982244
|
Filing Dt:
|
12/01/1997
|
|
Title:
|
PREFETCHING HINTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
09036684
|
Filing Dt:
|
03/09/1998
|
|
Title:
|
EXTERNAL CLOCK GENERATOR FOR A MICROPROCESSOR
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|
