|
Total properties:
18
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/28/1990
|
Application #:
|
06827269
|
Filing Dt:
|
02/06/1986
|
|
Title:
|
CUP CHIP HAVING CACHE TAG COMPARATOR AND ADDRESS TRANSLATION UNIT ON CHIP AND CONNECTED TO OFF-CHIP CACHE AND MAIN MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/14/1989
|
Application #:
|
06860304
|
Filing Dt:
|
05/05/1986
|
|
Title:
|
WRITE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/21/1989
|
Application #:
|
06945486
|
Filing Dt:
|
12/23/1986
|
|
Title:
|
RISC COMPUTER WITH UNALIGNED REFERENCE HANDLING AND METHOD FOR THE SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/07/1989
|
Application #:
|
07161543
|
Filing Dt:
|
02/29/1988
|
|
Title:
|
METHOD AND APPARATUS FOR PRECISE FLOATING POINT EXCEPTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1991
|
Application #:
|
07255791
|
Filing Dt:
|
10/11/1988
|
|
Title:
|
PROCESSOR CONTROLLED INTERFACE WITH INSTRUCTION STREAMING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/25/1990
|
Application #:
|
07277406
|
Filing Dt:
|
11/28/1988
|
|
Title:
|
DUAL BYTE ORDER COMPUTER ARCHITECTURE A FUNCTIONAL UNIT FOR HANDLING DATA SETS WITH DIFFERENT BYTE ORDERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1993
|
Application #:
|
07444594
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
TWO-LEVEL TRANSLATION LOOK-ASIDE BUFFER USING PARTIAL ADDRESSES FOR ENHANCED SPEED
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/12/1993
|
Application #:
|
07444633
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
SLOT DETERMINATION MECHANISM USING PULSE COUNTING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/1992
|
Application #:
|
07444639
|
Filing Dt:
|
12/01/1989
|
|
Title:
|
INTERRUPT REPORTING FOR SINGLE-BIT MEMORY ERRORS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/08/1991
|
Application #:
|
07448715
|
Filing Dt:
|
12/11/1989
|
|
Title:
|
DIFFERENTIAL BUS WITH SPECIFIED DEFAULT VALUE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/08/1994
|
Application #:
|
07573926
|
Filing Dt:
|
08/28/1990
|
|
Title:
|
LOW-NOISE HIGH-SPEED OUTPUT BUFFER AND METH0D FOR CONTROLLING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1993
|
Application #:
|
07644705
|
Filing Dt:
|
01/23/1991
|
|
Title:
|
VARIABLE PAGE SIZE PER ENTRY TRANSLATION LOOK-ASIDE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/31/1992
|
Application #:
|
07659526
|
Filing Dt:
|
02/22/1991
|
|
Title:
|
VARIABLE DELAY LINE PHASE-LOCKED LOOP CIRCUIT SYNCHRONIZATION SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/1994
|
Application #:
|
07892918
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
SENSE AMP FOR BIT LINE SENSING AND DATA LATCHING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/05/1994
|
Application #:
|
07892919
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
REDUNDANCY SELECTION APPARATUS AND METHOD FOR AN ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/05/1994
|
Application #:
|
07893156
|
Filing Dt:
|
06/03/1992
|
|
Title:
|
REDUNDANT ELEMENT SUBSTITUTION APPARATUS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/26/1994
|
Application #:
|
08059715
|
Filing Dt:
|
05/10/1993
|
|
Title:
|
CACHE MEMORY SYSTEM EMPLOYING VIRTUAL ADDRESS PRIMARY INSTRUCTION AND DATA CACHES AND PHYSICAL ADDRESS SECONDARY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/30/1995
|
Application #:
|
08223388
|
Filing Dt:
|
04/05/1994
|
|
Title:
|
BACKWARD-COMPATIBLE COMPUTER ARCHITECTURE WITH EXTENDED WORD SIZE AND ADDRESS SPACE
|
|
