Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 009695/0534 | |
| Pages: | 4 |
| | Recorded: | 01/05/1999 | | |
| Conveyance: | SEE RECORDING AT REEL 9804, FRAME 0961. RE-RECORD TO CORRECT THE RECORDATION DATE. |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/18/2003
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Application #:
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09128057
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Filing Dt:
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07/29/1998
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Publication #:
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Pub Dt:
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11/15/2001
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Title:
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METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25 MICRON AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES PRIOR TO ILD DEPOSITION AND SEMICONDUCTOR CHIP MADE THEREBY
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Assignee
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| ONE AMD PLACE, M/S 68 |
| SUNNYVALE, CALIFORNIA 94088 |
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Correspondence name and address
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LA RIVIERE GRUBMAN & PAYNE
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VICTOR FLORES
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4 JUSTIN COURT, SUITE A
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MONTEREY, CA 93940
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