|
Total properties:
77
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/13/1994
|
Application #:
|
08023656
|
Filing Dt:
|
02/26/1993
|
|
Title:
|
FABRIC EQUIPMENT GUARD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/1996
|
Application #:
|
08200216
|
Filing Dt:
|
02/23/1994
|
|
Title:
|
FERROELECTRIC CAPACITOR RENEWAL METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/04/1996
|
Application #:
|
08238802
|
Filing Dt:
|
05/06/1994
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A TRANSISTOR, A FERROELECTRIC CAPACITOR AND A HYDROGEN BARRIER FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/26/1995
|
Application #:
|
08254281
|
Filing Dt:
|
06/06/1994
|
|
Title:
|
NOISE AND GLITCH SUPPRESSING FILTER WITH FEEDBACK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/11/1997
|
Application #:
|
08267278
|
Filing Dt:
|
06/28/1994
|
|
Title:
|
PROCESS FOR FABRICATING TRANSISTORS USING COMPOSITE NITRIDE STRUCTURE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/15/1996
|
Application #:
|
08284384
|
Filing Dt:
|
08/02/1994
|
|
Title:
|
CIRCUIT WITH A SINGLE ADDRESS REGISTER THAT AUGMENTS A MEMORY CONTROLLER BY ENABLING CACHE READS AND PAGE-MODE WRITES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/12/1996
|
Application #:
|
08294833
|
Filing Dt:
|
08/29/1994
|
|
Title:
|
DEVICE FOR SIDETRACKING A TRUCK
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/1995
|
Application #:
|
08303134
|
Filing Dt:
|
09/08/1994
|
|
Title:
|
SEMICONDUCTOR DEVICE WITH A CONDUCTIVE REACTION-PREVENTING FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/05/1996
|
Application #:
|
08306686
|
Filing Dt:
|
09/16/1994
|
|
Title:
|
VOLTAGE REFERENCE FOR A FERROELECTRIC 1T/1C BASED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/16/1997
|
Application #:
|
08319289
|
Filing Dt:
|
10/06/1994
|
|
Title:
|
ENHANCED DRAM WITH ALL READS FROM ON-CHIP CACHE AND ALL WRITERS TO MEMORY ARRAY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/26/1996
|
Application #:
|
08394467
|
Filing Dt:
|
02/27/1995
|
|
Title:
|
PASSIVATION METHOD AND STRUCTURE USING HARD CERAMIC MATERIALS OR THE LIKE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/21/1996
|
Application #:
|
08403489
|
Filing Dt:
|
03/14/1995
|
|
Title:
|
FILM HAVING FERROELECTRIC BISMUTH LAYERED OXIDES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/02/1996
|
Application #:
|
08413083
|
Filing Dt:
|
03/29/1995
|
|
Title:
|
FERROELECTRIC MEMORY SENSING METHOD USING DISTINCT READ AND WRITE VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/07/1997
|
Application #:
|
08420293
|
Filing Dt:
|
04/10/1995
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING A COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/25/1996
|
Application #:
|
08420752
|
Filing Dt:
|
04/12/1995
|
|
Title:
|
FERROELECTRIC MEMORY SENSING SCHEME USING BIT LINES PRECHARGED TO A LOGIC ONE VOLTAGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/04/1998
|
Application #:
|
08428544
|
Filing Dt:
|
04/25/1995
|
|
Title:
|
FABRICATION OF METAL-FERROELECTRIC-METAL CAPACITORS WITH A TWO STEP PATTERNING SEQUENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/24/1998
|
Application #:
|
08460665
|
Filing Dt:
|
06/02/1995
|
|
Title:
|
ENHANCED DRAM WITH SINGLE ROW SRAM CACHE FOR ALL DEVICE READ OPERATIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/28/1997
|
Application #:
|
08515558
|
Filing Dt:
|
08/16/1995
|
|
Title:
|
FERROELECTRIC NONVOLATILE RANDOM ACCESS MEMORY UTILIZING SELF-BOOTSTRAPPING PLATE LINE SEGMENT DRIVERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/20/1999
|
Application #:
|
08521251
|
Filing Dt:
|
08/30/1995
|
|
Title:
|
PROGRAMMABLE OUTPUT DEVICES FOR CONTROLLING SIGNAL LEVELS IN AN RF/ID TRANSPONDER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08521597
|
Filing Dt:
|
08/30/1995
|
|
Title:
|
MULTIBUS CACHED MEMORY SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/04/1997
|
Application #:
|
08525497
|
Filing Dt:
|
09/08/1995
|
|
Title:
|
INTEGRATION OF HIGH VALUE CAPACITOR WITH FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/03/1996
|
Application #:
|
08527175
|
Filing Dt:
|
09/11/1995
|
|
Title:
|
METHOD FOR MAKING A FERROELECTRRIC MEMORY CELL WITH A FERROELECTRIC CAPACITOR OVERLYING A MEMORY TRANSISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/01/1999
|
Application #:
|
08544470
|
Filing Dt:
|
10/18/1995
|
|
Title:
|
METHOD OF MAKING INTEGRATION OF HIGH VALUE CAPACITOR WITH FERRO- ELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/23/1999
|
Application #:
|
08615392
|
Filing Dt:
|
03/14/1996
|
|
Title:
|
COMPUTER HYBRID MEMORY INCLUDING DRAM AND EDRAM MEMORY COMPONENTS, WITH SECONDARY CACHE IN EDRAM FOR DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08616856
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
USE OF CALCIUM AND STRONTIUM DOPANTS TO IMPROVE RETENTION PERFORMANCE IN A PZT FERROELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/28/1999
|
Application #:
|
08616913
|
Filing Dt:
|
03/15/1996
|
|
Title:
|
METHOD OF MEASURING RETENTION PERFORMANCE AND IMPRINT DEGRADATION OF FERROELECTRIC FILMS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/17/1998
|
Application #:
|
08618884
|
Filing Dt:
|
03/20/1996
|
|
Title:
|
IRIDIUM OXIDE LOCAL INTERCONNECT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/10/1998
|
Application #:
|
08620450
|
Filing Dt:
|
03/22/1996
|
|
Title:
|
EDRAM WITH INTEGRATED GENERATION AND CONTROL OF WRITE ENABLE AND COLUMN LATCH SIGNALS AND METHOD FOR MAKING SAME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/30/1998
|
Application #:
|
08620799
|
Filing Dt:
|
03/28/1996
|
|
Title:
|
BOOTSTRAPPING CIRCUIT UTILIZING A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/09/1999
|
Application #:
|
08630489
|
Filing Dt:
|
04/10/1996
|
|
Title:
|
ED RAM HAVING A DYNAMICALLY-SIZED CACHE MEMORY AND ASSOCIATED METHOD THEREOF
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/13/1998
|
Application #:
|
08634445
|
Filing Dt:
|
04/18/1996
|
|
Title:
|
VOLTAGE REFERENCE FOR A FERROELECTRIC 1T/IC BASED MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/07/1999
|
Application #:
|
08663032
|
Filing Dt:
|
06/07/1996
|
|
Title:
|
LOW VOLTAGE BOOTSTRAPPING CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/29/1998
|
Application #:
|
08691132
|
Filing Dt:
|
08/01/1996
|
|
Title:
|
CIRCUIT AND METHOD FOR REDUCING COMPENSATION OF A FERROELECTRIC CAPACITOR BY MULTIPLE PULSING OF THE PLATE LINE FOLLOWING A WRITE OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/06/1999
|
Application #:
|
08700076
|
Filing Dt:
|
08/20/1996
|
|
Title:
|
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/22/1998
|
Application #:
|
08702363
|
Filing Dt:
|
08/23/1996
|
|
Title:
|
BANDGAP REFERENCE BASED POWER-ON DETECT CIRCUIT INCLUDING A SUPRESSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/06/1998
|
Application #:
|
08723367
|
Filing Dt:
|
09/30/1996
|
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/26/1997
|
Application #:
|
08723935
|
Filing Dt:
|
09/27/1996
|
|
Title:
|
SAME STATE AND OPPOSITE STATE DIAGNOSTIC TEST FOR FERROELECTRIC MEMORIES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08728256
|
Filing Dt:
|
10/08/1996
|
|
Title:
|
YIELD ENHANCEMENT TECHNIQUE FOR INTEGRATED CIRCUIT PROCESSING TO REDUCE EFFECTS OF UNDESIRED DIELECTRIC MOISTURE RETENTION AND SUBSEQUENT HYDROGEN OUT-DIFFUSION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
08728740
|
Filing Dt:
|
10/11/1996
|
|
Title:
|
PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/30/1999
|
Application #:
|
08734802
|
Filing Dt:
|
10/21/1996
|
|
Title:
|
DATA PROCESSOR INCORPORATING A FERROELECTRIC MEMORY ARRAY SELECTABLY CONFIGURABLE AS READ/WRITE AND READ ONLY MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08745581
|
Filing Dt:
|
10/30/1996
|
|
Title:
|
SYSTEM AND METHOD PROVIDING SELECTIVE WRITE PROTECTION FOR INDIVIDUAL BLOCKS OF MEMORY IN A NON-VOLATILE MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/1998
|
Application #:
|
08799999
|
Filing Dt:
|
02/13/1997
|
|
Title:
|
LOW-POWER NON-RESETABLE TEST MODE CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/15/1999
|
Application #:
|
08810607
|
Filing Dt:
|
02/28/1997
|
|
Title:
|
SERIAL FERROELECTRIC RANDOM ACCESS MEMORY ARCHITECTURE TO EQUALIZE COLUMN ACCESSES AND IMPROVE DATA RETENTION RELIABILITY BY MITIGATING IMPRINT EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/28/1998
|
Application #:
|
08810608
|
Filing Dt:
|
02/28/1997
|
|
Title:
|
SYSTEM AND METHOD FOR MITIGATING IMPRINT EFFECT IN FERROELECTRIC RANDOM ACCESS MEMORIES UTILIZING A COMPLEMENTARY DATA PATH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08828157
|
Filing Dt:
|
03/27/1997
|
|
Title:
|
PARTIALLY OR COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
08840118
|
Filing Dt:
|
04/01/1997
|
|
Title:
|
FIRST-IN, FIRST-OUT INTEGRATED CIRCUIT MEMORY DEVICE UTILIZING A DYNAMIC RANDOM ACCESS MEMORY ARRAY FOR DATA STORAGE IMPLEMENTED IN CONJUCTION WITH AN ASSOCIATED STATIC RANDOM ACCESS MEMORY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08850802
|
Filing Dt:
|
05/02/1997
|
|
Title:
|
ENHANCED SIGNAL PROCESSING RANDOM ACCESS MEMORY DEVICE UTILIZING A DRAM MEMORY ARRAY INTEGRATED WITH AN ASSOCIATED SRAM CACHE AND INTERNAL REFRESH CONTROL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/11/1999
|
Application #:
|
08853527
|
Filing Dt:
|
05/09/1997
|
|
Title:
|
DUAL-LEVEL METALIZATION METHOD FOR INTEGRATED CIRCUIT FERROELECTRIC DEVICES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/01/1998
|
Application #:
|
08861674
|
Filing Dt:
|
05/22/1997
|
|
Title:
|
USE OF CALCIUM AND STRONTIUM DOPANTS TO IMPROVE RETENTION PERFORMANCE IN A PZT FERROELECTRIC FILM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/23/1999
|
Application #:
|
08888371
|
Filing Dt:
|
07/03/1997
|
|
Title:
|
ENHANCED DRAM WITH EMBEDDED REGISTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/27/2000
|
Application #:
|
08896684
|
Filing Dt:
|
07/18/1997
|
|
Title:
|
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/29/1998
|
Application #:
|
08915054
|
Filing Dt:
|
08/20/1997
|
|
Title:
|
VOLTAGE BOOST CIRCUIT AND OPERATION THEREOF AT LOW POWER SUPPLY VOLTAGES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/30/1999
|
Application #:
|
08970448
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
PLATE LINE SEGMENTATION IN A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/21/1999
|
Application #:
|
08970452
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/09/1999
|
Application #:
|
08970453
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSING METHODOLOGY FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/06/1999
|
Application #:
|
08970454
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
COLUMN DECODER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
08970518
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
REFERENCE CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/19/1999
|
Application #:
|
08970519
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSE AMPLIFIER CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/22/2000
|
Application #:
|
08970520
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
MEMORY CELL CONFIGURATION FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/14/1999
|
Application #:
|
08970521
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
SENSE AMPLIFIER LATCH DRIVER CIRCUIT FOR A 1T/1C ERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/02/1999
|
Application #:
|
08970522
|
Filing Dt:
|
11/14/1997
|
|
Title:
|
PLATE LINE DRIVER CIRCUIT FOR A 1T/1C FERROELECTRIC MEMORY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/02/1999
|
Application #:
|
09017577
|
Filing Dt:
|
02/03/1998
|
|
Title:
|
BANDGAP REFERENCE BASED POWER-ON DETECT CIRCUIT INCLUDING A SUPPRESSION CIRCUIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09021132
|
Filing Dt:
|
02/10/1998
|
|
Title:
|
INTEGRATED CIRCUIT MEMORY DEVICE INCORPORATING A NON-VOLATILE MEMORY ARRAY AND A RELATIVELY FASTER ACCESS TIME MEMORY CACHE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/04/1999
|
Application #:
|
09022106
|
Filing Dt:
|
02/11/1998
|
|
Title:
|
SENSE AMPLIFIER UTILIZING A BALANCING RESISTOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09061362
|
Filing Dt:
|
04/15/1998
|
|
Title:
|
FERROELECTRIC THIN FILMS AND SOLUTIONS: COMPOSITIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/18/2000
|
Application #:
|
09064465
|
Filing Dt:
|
04/22/1998
|
|
Title:
|
MULTI-LAYER APPROACH FOR OPTIMIZING FERROELECTRIC FILM PERFORMANCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/31/2000
|
Application #:
|
09069468
|
Filing Dt:
|
04/29/1998
|
|
Title:
|
TECHNIQUE FOR REDUCING ELEMENT DISABLE FUSE PITCH REQUIREMENTS IN AN INTEGRATED CIRCUIT DEVICE INCORPORATING REPLACEABLE CIRCUIT ELEMENTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2001
|
Application #:
|
09085280
|
Filing Dt:
|
05/27/1998
|
|
Title:
|
COMPLETELY ENCAPSULATED TOP ELECTRODE OF A FERROELECTRIC CAPACITOR USING A LEAD-ENHANCED ESCAPSULATION LAYER
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|
|
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Patent #:
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Issue Dt:
|
08/01/2000
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Application #:
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09087726
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Filing Dt:
|
05/29/1998
|
|
Title:
|
CMOS RC EQUIVALENT DELAY CIRCUIT
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|
|
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Patent #:
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Issue Dt:
|
10/05/1999
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Application #:
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09108089
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Filing Dt:
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06/30/1998
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Title:
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EMBEDDED ENHANCED DRAM, AND ASSOCIATED METHOD
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/16/2000
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Application #:
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09111822
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Filing Dt:
|
07/08/1998
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Title:
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MULTI-ARRAY MEMORY DEVICE, AND ASSOCIATED METHOD, HAVING SHARED DECODER CIRCUITRY
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|
|
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Patent #:
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|
Issue Dt:
|
04/25/2000
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Application #:
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09146726
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Filing Dt:
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09/03/1998
|
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Title:
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DYNAMIC RANDOM ACCESS MEMORY WORD LINE BOOST TECHNIQUE EMPLOYING A BOOST-ON-WRITES POLICY
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|
|
|
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Patent #:
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|
Issue Dt:
|
06/19/2001
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Application #:
|
09164952
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Filing Dt:
|
10/01/1998
|
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Title:
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HYDROGEN BARRIER ENCAPSULATION TECHNIQUES FOR THE CONTROL OF HYDROGEN INDUCED DEGRADATION OF FERROELECTRIC CAPACITORS IN CONJUNCTION WITH MULTILEVEL METAL PROCESSING FOR NON-VOLATILE INTEGRATED CIRCUIT MEMORY DEVICES
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
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Application #:
|
09177392
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Filing Dt:
|
10/23/1998
|
|
Title:
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METHOD OF MANUFACTURING FERROELECTRIC MEMORY DEVICE USEFUL FOR PREVENTING HYDROGEN LINE DEGRADATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/19/2001
|
Application #:
|
09178298
|
Filing Dt:
|
10/23/1998
|
|
Title:
|
MULTI-BANK ESDRAM WITH CROSS -COUPLED SRAM CACHE REGISTERS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
02/12/2002
|
Application #:
|
09182994
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Filing Dt:
|
10/30/1998
|
|
Title:
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ENHANCED DRAM WITH EMBEDDED REGISTERS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/16/1999
|
Application #:
|
09183545
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Filing Dt:
|
10/29/1998
|
|
Title:
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METHOD OF FORMING OXIDE LOCAL INTERCONNECT
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|
