Patent Assignment Details
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| Reel/Frame: | 009983/0446 | |
| Pages: | 3 |
| | Recorded: | 05/27/1999 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09265876
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Filing Dt:
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03/11/1999
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF ESTIMATING FAILURE RATIO OF SUCH DEVICES ON THE MARKET, AND METHOD OF MANUFACTURING THE DEVICES
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Assignee
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| 72 HORIKAWA-CHO, SAIWAI-KU |
| KAWASAKI-SHI, JAPAN |
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Correspondence name and address
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FINNEGAN, HENDERSON, FARABOW ET AL.
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ERNEST F. CHAPMAN
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1300 I STREET, N.W.
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WASHINGTON, D.C. 20005
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