Patent Assignment Details
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Reel/Frame: | 010030/0081 | |
| Pages: | 4 |
| | Recorded: | 06/11/1999 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09270918
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Filing Dt:
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03/16/1999
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Title:
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PARALLEL/PIPELINE VLSI ARCHITECTURE FOR A LOW-DELAY CELP CODER/DECODER
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Assignee
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BUILDING 001, M/S A109 |
200 NORTH SEPULVEDA BOULEVARD, P.O. BOX 956 |
EL SEGUNDO, CALIFORNIA 90245 |
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Correspondence name and address
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HUGHES ELECTRONICS CORPORATION
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JOHN T. WHELAND
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BUILDING 001, M/S A109, P.O. BOX 956
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200 NORTH SEPULVEDA BOULEVARD
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EL SEGUNDO, CA 90245-0956
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