Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 010197/0730 | |
| Pages: | 2 |
| | Recorded: | 09/03/1999 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
2
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Patent #:
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Issue Dt:
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06/20/1995
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Application #:
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07797936
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Filing Dt:
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11/26/1991
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Title:
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SEQUENTIAL LOGIC CIRCUIT HAVING STATE HOLD CIRCUITS
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Patent #:
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Issue Dt:
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08/01/1995
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Application #:
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08299669
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Filing Dt:
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09/02/1994
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Title:
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MEMORY DEVICE, METHOD FOR READING INFORMATION FROM THE MEMORY DEVICE, METHOD FOR WRITING INFORMATION INTO THE MEMORY DEVICE, AND METHOD FOR PRODUCING THE MEMORY DEVICE
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Assignee
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1-1 HIGASHI-IKEBUKURO 3-CHOME |
SUNSHINE 60 BUILDING |
TOSHIMA-KU, TOKYO 170-6028, JAPAN |
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Correspondence name and address
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STAAS & HALSEY LLP
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H.J. STAAS
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700 ELEVENTH STREET, N.W., SUITE 500
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WASHINGTON, D.C. 20001
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