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12/19/1978
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05/02/1977
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12/31/1985
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08/19/1983
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08/26/1986
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12/23/1983
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03/31/1987
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01/06/1984
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08/04/1987
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07/20/1984
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02/24/1987
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09/18/1984
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03/31/1987
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12/18/1984
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01/06/1987
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12/18/1984
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05/03/1988
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04/26/1985
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05/03/1988
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09/26/1985
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10/24/1989
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02/07/1986
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10/18/1988
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07/02/1986
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02/16/1988
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12/05/1986
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08/15/1989
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02/29/1988
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01/02/1990
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05/11/1988
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08/02/1988
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06/12/1990
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05/24/1989
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09/21/1993
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05/08/1990
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05/28/1991
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09/13/1990
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06/23/1992
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02/14/1991
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03/19/1993
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10/29/1996
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05/30/1995
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12/10/1996
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05/30/1995
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05/19/1998
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06/06/1995
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06/06/1995
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06/07/1995
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10/15/1996
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06/23/1995
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09/15/1998
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12/18/1995
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02/17/1998
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12/20/1995
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07/20/1999
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03/13/1996
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05/15/1997
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08/18/1997
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03/19/2002
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09/16/1997
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08/01/2000
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10/09/1997
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11/23/1999
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12/22/1997
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11/09/1999
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12/22/1997
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03/07/2000
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12/22/1997
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12/22/1997
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11/16/1999
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12/22/1997
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08/14/2001
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12/22/1997
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08/22/2000
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12/22/1997
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10/10/2000
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01/19/1998
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02/10/1998
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10/03/2000
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03/09/1998
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11/09/1999
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03/23/1998
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02/22/2000
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07/13/1998
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07/18/2000
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07/13/1998
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03/28/2000
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07/13/1998
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02/22/2000
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07/17/1998
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05/16/2000
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11/28/2000
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11/09/1998
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09/18/2001
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11/13/1998
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04/24/2001
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11/13/1998
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11/24/1998
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03/05/2002
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11/25/1998
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07/17/2001
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11/24/1998
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Filing Dt:
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11/30/1998
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Title:
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PHASE LOCKED LOOP WITH A LOCK DETECTOR
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Patent #:
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Issue Dt:
|
06/11/2002
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Application #:
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09203149
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Filing Dt:
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12/01/1998
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Publication #:
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Pub Dt:
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10/18/2001
| | | | |
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Title:
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EEPROM CELL WITH TUNNELING ACROSS ENTIRE SEPARATED CHANNELS
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Patent #:
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Issue Dt:
|
12/19/2000
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Application #:
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09208203
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Filing Dt:
|
12/09/1998
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Title:
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EFFICIENT INTERCONNECT NETWORK FOR USE IN FPGA DEVICE HAVING VARIABLE GRAIN ARCHITECTURE
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Patent #:
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Issue Dt:
|
06/27/2000
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Application #:
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09212331
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Filing Dt:
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12/15/1998
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Title:
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FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS EACH WITH STATICALLY AND DYNAMICALLY CONTROLLABLE READ MODE
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Patent #:
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Issue Dt:
|
04/10/2001
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Application #:
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09216051
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Filing Dt:
|
12/18/1998
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Title:
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METHOD OF FORMING A NON-VOLATILE MEMORY DEVICE
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Patent #:
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Issue Dt:
|
03/20/2001
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Application #:
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09216662
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Filing Dt:
|
12/16/1998
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Title:
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METHODS FOR CONFIGURING FPGA'S HAVING VARIABLE GRAIN BLOCKS AND SHARED LOGIC FOR PROVIDING SYMMETRIC ROUTING OF RESULT OUTPUT TO DIFFERENTLY-DIRECTED AND TRISTATEABLE INTERCONNECT RESOURCES
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Patent #:
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Issue Dt:
|
08/28/2001
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Application #:
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09217646
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Filing Dt:
|
12/21/1998
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Title:
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METHOD OF FABRICATING PROGRAMMING AND ERASING A DUAL POCKET TWO
SIDED PROGRAM/ERASE NON-VOLATILE MEMORY CELL
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Patent #:
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Issue Dt:
|
10/19/1999
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Application #:
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09217647
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Filing Dt:
|
12/21/1998
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|
Title:
|
EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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|
|
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Patent #:
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Issue Dt:
|
05/15/2001
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Application #:
|
09217648
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Filing Dt:
|
12/21/1998
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|
Title:
|
FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAMMING MECHANISM OUTSIDE THE READ PATH
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|
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Patent #:
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|
Issue Dt:
|
09/25/2001
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Application #:
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09218987
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Filing Dt:
|
12/22/1998
|
|
Title:
|
EEPROM CELL WITH TUNNELING AT SEPARATE EDGE AND CHANNEL REGIONS
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|
|
|
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Patent #:
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|
Issue Dt:
|
05/16/2000
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Application #:
|
09220201
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Filing Dt:
|
12/23/1998
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|
Title:
|
FLOATING GATE MEMORY APPARATUS AND METHOD FOR SELECTED PROGRAMMING THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
12/05/2000
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Application #:
|
09220469
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Filing Dt:
|
12/23/1998
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|
Title:
|
AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN FIRST POLYSILICON LAYER
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|
|
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Patent #:
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|
Issue Dt:
|
09/25/2001
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Application #:
|
09221360
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Filing Dt:
|
12/28/1998
|
|
Title:
|
AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE WITH PROGRAM ELEMENT IN POLYSILICON
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|
|
|
|
Patent #:
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|
Issue Dt:
|
04/10/2001
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Application #:
|
09226702
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Filing Dt:
|
01/07/1999
|
|
Title:
|
PMOS AVALANCHE PROGRAMMED FLOATING GATE MEMORY CELL STRUCTURE
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|
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Patent #:
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|
Issue Dt:
|
03/06/2001
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Application #:
|
09227981
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Filing Dt:
|
01/08/1999
|
|
Title:
|
OXIDE FORMATION PROCESS FOR MANUFACTURING PROGRAMMABLE LOGIC DEVICE
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|
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|
Patent #:
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|
Issue Dt:
|
01/30/2001
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Application #:
|
09235351
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Filing Dt:
|
01/21/1999
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|
Title:
|
FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS AND INTERCONNECT CHANNEL FOR BROADCASTING ADDRESS AND CONTROL SIGNALS
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|
|
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Patent #:
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|
Issue Dt:
|
08/01/2000
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Application #:
|
09235356
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Filing Dt:
|
01/21/1999
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Title:
|
MULTI-PORT SRAM CELL ARRAY HAVING PLURAL WRITE PATHS INCLUDING FOR WRITING THROUGH ADDRESSABLE PORT AND THROUGH SERIAL BOUNDARY SCAN
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Patent #:
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|
Issue Dt:
|
04/03/2001
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Application #:
|
09235615
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Filing Dt:
|
01/21/1999
|
|
Title:
|
FPGA INTEGRATED CIRCUIT HAVING EMBEDDED SRAM MEMORY BLOCKS WITH REGISTERED ADDRESS AND DATA INPUT SECTIONS
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Patent #:
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Issue Dt:
|
12/07/1999
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Application #:
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09239072
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Filing Dt:
|
01/27/1999
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|
Title:
|
TWO TRANSISTOR EEPROM CELL USING P-WELL FOR TUNNELING ACROSS A CHANNEL
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Patent #:
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Issue Dt:
|
10/02/2001
|
Application #:
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09240560
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Filing Dt:
|
01/29/1999
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|
Title:
|
PROCESS FOR MANUFACTURING SHALLOW TRENCHES FILLED WITH DIELECTRIC MATERIAL HAVING LOW MECHANICAL STRESS
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Patent #:
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Issue Dt:
|
09/25/2001
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Application #:
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09245813
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Filing Dt:
|
02/05/1999
|
|
Title:
|
TWO TRANSISTOR EEPROM CELL
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Patent #:
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|
Issue Dt:
|
07/03/2001
|
Application #:
|
09255053
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Filing Dt:
|
02/22/1999
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|
Title:
|
PROCESS FOR FABRICATING A HIGH-ENDURANCE NON-VOLATILE MEMORY DEVICE
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Patent #:
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|
Issue Dt:
|
06/13/2000
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Application #:
|
09263412
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Filing Dt:
|
03/05/1999
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING A MULTI-LAYER METAL INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
|
03/27/2001
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Application #:
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09266245
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Filing Dt:
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03/10/1999
|
|
Title:
|
METHOD AND APPARATUS FOR ASSIGNING SPECTRUM OF A LOCAL AREA NETWORK
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09268897
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Filing Dt:
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03/16/1999
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|
Title:
|
NON-VOLATILE MEMORY DEVICE HAVING A HIGH-RELIABILITY COMPOSITE INSULATON LAYER
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Patent #:
|
NONE
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Issue Dt:
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|
Application #:
|
09276068
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Filing Dt:
|
03/25/1999
|
|
Publication #:
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|
Pub Dt:
|
02/14/2002
| | | | |
|
Title:
|
FARICATION OF HIGH QUALITY OXIDES BY CONTROLLING SPACING BETWEEN SEMICONDUCTOR WAFERS DURING PROCESSING
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Patent #:
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Issue Dt:
|
12/04/2001
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Application #:
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09277441
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Filing Dt:
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03/26/1999
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Title:
|
AVALANCHE INJECTION EEPROM MEMORY CELL WITH P-TYPE CONTROL GATE
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Patent #:
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Issue Dt:
|
01/09/2001
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Application #:
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09280887
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Filing Dt:
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03/29/1999
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Title:
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BORON DOPED SILICON CAPACITOR PLATE
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Patent #:
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Issue Dt:
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09/04/2001
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Application #:
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09286830
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Filing Dt:
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04/06/1999
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Title:
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ANGLED NITROGEN ION IMPLANTATION FOR MINIMIZING MECHANICAL STRESS ON SIDE WALLS OF AN ISOLATION TRENCH
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Patent #:
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Issue Dt:
|
07/02/2002
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Application #:
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09287976
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Filing Dt:
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04/07/1999
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Publication #:
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Pub Dt:
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01/24/2002
| | | | |
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Title:
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HIGH DIELECTRIC GATE INSULATOR PROCESS FOR NANOMETER MOSFETS
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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09998978
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Filing Dt:
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11/15/2001
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Publication #:
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Pub Dt:
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09/05/2002
| | | | |
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Title:
|
APPARATUS AND METHOD FOR LOADING A PROSTHETIC NUCLEUS INTO A DEPLOYMENT CANNULA TO REPLACE THE NUCLEUS PULPOSUS OF AN INTERVERTEBRAL DISC
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