Patent Assignment Details
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| Reel/Frame: | 010315/0127 | |
| Pages: | 2 |
| | Recorded: | 10/06/1999 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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11/05/2002
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Application #:
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09412986
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Filing Dt:
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10/06/1999
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Publication #:
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Pub Dt:
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08/16/2001
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Title:
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LAYOUT DESIGN METHOD ON SEMICONDUCTOR CHIP FOR AVOIDING DETOUR WIRING
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Assignee
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| 1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU, KAWASAKI-SHI |
| KANAGAWA 211-8588, JAPAN |
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Correspondence name and address
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NIKAIDO, MARMELSTEIN, MURRAY ET AL
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METROPOLITAN SQUARE
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655 15TH ST., N.W.
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SUITE 330 - G STREET LOBBY
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WASHINGTON, DC 20005-5701
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