Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 010557/0773 | |
| Pages: | 9 |
| | Recorded: | 02/03/2000 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
8
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Patent #:
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Issue Dt:
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05/19/1998
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Application #:
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08466438
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Filing Dt:
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06/06/1995
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Title:
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LOW POWER CMOS ARRAY CELL FOR A PLD WITH PROGRAM AND ERASE USING CONTROLLED AVALANCHE INJECTION
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Patent #:
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Issue Dt:
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04/21/1998
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Application #:
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08497992
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Filing Dt:
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07/03/1995
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Title:
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NON-VOLATILE MEMORY CELLS USING ONLY POSITIVE CHARGE TO STORE DATA
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Patent #:
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Issue Dt:
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12/23/1997
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Application #:
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08500295
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Filing Dt:
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07/10/1995
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Title:
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METHOD FOR SCREENING NON-VOLATILE MEMORY AND PROGRAMMABLE LOGIC DEVICES
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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08560038
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Filing Dt:
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11/17/1995
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Title:
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MEMORY CELL FOR A PROGRAMMABLE LOGIC DEVICE (PLD) AVOIDING PUMPING PROGRAMMING VOLTAGE ABOVE AN NMOS THRESHOLD
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Patent #:
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Issue Dt:
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09/30/1997
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Application #:
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08561306
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Filing Dt:
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11/21/1995
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Title:
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METHOD OF FORMING MULTIPLE GATE OXIDE THICKNESSES ON A WAFER SUBSTRATE
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08664190
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Filing Dt:
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06/10/1996
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Title:
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SIMPLIFIED MASKING PROCESS FOR PROGRAMMABLE LOGIC DEVICE MANUFACTURE
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Patent #:
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Issue Dt:
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06/02/1998
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Application #:
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08726512
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Filing Dt:
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10/07/1996
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Title:
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A VPP ONLY SCALABLE EEPROM MEMORY CELL HAVING TRANSISTORS WITH THIN TUNNEL GATE OXIDE
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Patent #:
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Issue Dt:
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11/24/1998
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Application #:
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08785096
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Filing Dt:
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01/21/1997
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Title:
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METHOD OF CHARGING AND DISCHARGING FLOATING GATE TRANSISTORS TO REDUCE LEAKAGE CURRENT
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Assignee
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| ONE AMD PLACE |
| SUNNYVALE, CALIFORNIA 94088 |
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Correspondence name and address
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O'MELVENY & MYERS LLP
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CHRISTINA WH CHANG
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400 SOUTH HOPE STREET
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LOS ANGELES, CA 90071
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