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Patent Assignment Details
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Reel/Frame:010619/0715   Pages: 5
Recorded: 02/11/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
07/03/2001
Application #:
09503634
Filing Dt:
02/14/2000
Title:
Method of forming a gate structure of a transistor by means of scalable spacer technology
Assignors
1
Exec Dt:
02/01/2000
2
Exec Dt:
02/01/2000
3
Exec Dt:
02/09/2000
Assignee
1
5204 E. BEN WHITE BLVD.
AUSTIN, TEXAS 78741
Correspondence name and address
WILLIAMS, MORGAN & AMERSON, P.C.
J. MIKE AMERSON
7676 HILLMONT, SUITE 250
HOUSTON, TEXAS 77040

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