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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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08985698
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Filing Dt:
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12/05/1997
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Title:
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METHOD FOR MANUFACTURING INTERCONNECTION PLUG
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Patent #:
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Issue Dt:
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11/09/1999
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Application #:
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08999235
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Filing Dt:
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12/29/1997
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Title:
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METHOD FOR MANUFACTURING INTERCONNECTION PLUG
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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09041827
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Filing Dt:
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03/12/1998
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Title:
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METHOD FOR MAKING A FLOWER SHAPED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09041863
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Filing Dt:
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03/12/1998
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Title:
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METHOD FOR MAKING A DRAM CAPACITOR USING A DOUBLE LAYER OF INSITU DOPED POLYSILICON AND UNDOPED AMORPHOUS POLYSILICON WITH HSG POLYSILICON
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Patent #:
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Issue Dt:
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08/03/1999
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Application #:
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09041864
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Filing Dt:
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03/12/1998
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Title:
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METHOD FOR FORMING A PLANAR INTERMETAL DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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09050622
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Filing Dt:
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03/30/1998
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Title:
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SINGLE POLY CYLINDRICAL FLASH MEMORY CELL HAVING HIGH COUPLING RATIO
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Patent #:
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Issue Dt:
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03/13/2001
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Application #:
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09050740
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Filing Dt:
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03/30/1998
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Title:
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METHOD FOR AUTOMATICALLY DETERMINING ADJUSTMENTS FOR STEPPING PHOTOLITHOGRAPHY EXPOSURES
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09050741
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Filing Dt:
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03/30/1998
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Title:
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MULTI-LEVEL FLASH MEMORY USING TRIPLE WELL
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09060771
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Filing Dt:
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04/15/1998
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Title:
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DISHING FREE PROCESS FOR SHALLOW TRENCH ISOLATION
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09061618
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Filing Dt:
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04/16/1998
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Title:
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METHOD FOR MANUFACTURING SPLIT-GATE FLASH MEMORY CELL
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Patent #:
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Issue Dt:
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05/23/2000
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Application #:
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09063032
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Filing Dt:
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04/20/1998
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Title:
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METHOD OF FABRICATING SPLIT-GATE SOURCE SIDE INJECTION FLASH EEPROM ARRAY
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09065369
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Filing Dt:
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04/23/1998
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Title:
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METHOD FOR MANUFACTURING ETOX CELL HAVING DAMAGE-FREE SOURCE REGION
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09065781
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Filing Dt:
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04/23/1998
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Title:
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ROM STRUCTURE AND METHOD OF MANUFACTURE
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09069711
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Filing Dt:
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04/29/1998
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Title:
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METHOD OF FORMING BARRIER LAYER FOR TUNGSTEN PLUGS IN INTERLAYER DIELECTRICS
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Patent #:
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Issue Dt:
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02/01/2000
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Application #:
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09085321
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Filing Dt:
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05/26/1998
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Title:
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METHOD FOR FORMING A PLANAR INTERMETAL DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09085322
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Filing Dt:
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05/26/1998
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Title:
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INSITU PLASMA CLEAN FOR TUNGSTEN ETCHING BACK
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09089875
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Filing Dt:
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06/03/1998
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Title:
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METHOD FOR FORMING A DUAL DAMASCENE CONTACT AND INTERCONNECT
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09096901
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Filing Dt:
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06/12/1998
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Title:
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INTERLAYER DIELECTRIC PLANARIZATION PROCESS
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09099975
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Filing Dt:
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06/19/1998
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Title:
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METHOD OF FABRICATING A SPLIT GATE STRUCTURE OF A FLASH MEMORY
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09108901
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Filing Dt:
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07/01/1998
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Title:
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METHOD FOR FORMING A DRAM CAPACITOR
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Patent #:
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Issue Dt:
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01/18/2000
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Application #:
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09111683
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Filing Dt:
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07/08/1998
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Title:
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REDUCTION OF OPTICAL PROXIMITY EFFECT OF BIT LINE PATTERN IN DRAM DEVICES
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Patent #:
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Issue Dt:
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08/22/2000
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Application #:
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09118170
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Filing Dt:
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07/17/1998
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Title:
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METHOD FOR MAKING A MUSHROOM SHAPED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09121021
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Filing Dt:
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07/22/1998
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Title:
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METHOD FOR MAKING A STACKED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09123305
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Filing Dt:
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07/28/1998
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Title:
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HOT CARRIER INJECTION PROGRAMMING AND NEGATIVE GATE VOLTAGE CHANNEL ERASE FLASH EEPROM STRUCTURE
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09128217
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Filing Dt:
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08/03/1998
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Title:
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METHOD FOR ERASING SPLIT-GATE FLASH MEMORY
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Patent #:
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Issue Dt:
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05/16/2000
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Application #:
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09156522
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Filing Dt:
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09/17/1998
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Title:
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INSTALLATION FOR IMPROVING CHEMICAL-MECHANICAL POLISHING OPERATION
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Patent #:
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Issue Dt:
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06/29/1999
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Application #:
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09170859
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Filing Dt:
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10/13/1998
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Title:
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METHOD FOR MAKING DUAL DAMASCENE CONTACT
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Patent #:
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Issue Dt:
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09/18/2001
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Application #:
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09170861
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Filing Dt:
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10/13/1998
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Title:
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METHOD FOR MAKING A STACK BOTTOM STORAGE NODE HAVING REDUCED CRYSTALLIZATION OF AMORPHOUS POLYSILICON
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09170863
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Filing Dt:
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10/13/1998
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Title:
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SINGLE POLYSILICON DRAM CELL WITH CURRENT GAIN AND METHOD OF MAKING
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09177786
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Filing Dt:
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10/22/1998
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Title:
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LOW VOLTAGE LOW POWER N-CHANNEL FLASH MEMORY CELL USING GATE INDUCED DRAIN LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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11/07/2000
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Application #:
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09177787
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Filing Dt:
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10/22/1998
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Title:
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CMOS INVERTER USING GATE INDUCED DRAIN LEAKAGE CURRENT
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Patent #:
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Issue Dt:
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03/07/2000
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Application #:
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09189066
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Filing Dt:
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11/09/1998
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Title:
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METHOD FOR MAKING AN 8-SHAPED STORAGE NODE DRAM CELL
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09189067
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Filing Dt:
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11/09/1998
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Title:
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METHOD FOR MANUFACTURING A SELF-ALIGNED STACKED STORAGE NODE DRAM CELL
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Patent #:
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Issue Dt:
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08/08/2000
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Application #:
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09189353
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Filing Dt:
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11/09/1998
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Title:
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METHOD FOR MAKING FIN-TRENCH STRUCTURED DRAM CAPACITOR
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Patent #:
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Issue Dt:
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08/15/2000
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Application #:
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09200174
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Filing Dt:
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11/25/1998
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Title:
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WAFER CLEANING DEVICE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09200364
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Filing Dt:
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11/25/1998
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Title:
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INSTALLATION FOR IMPROVING CHEMICAL-MECHANICAL POLISHING OPERATION
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09201280
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Filing Dt:
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11/30/1998
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Title:
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METHOD FOR FORMING A CROWN CAPACITOR
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Patent #:
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Issue Dt:
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01/09/2001
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Application #:
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09201513
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Filing Dt:
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11/30/1998
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Title:
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METHOD FOR FORMING A PLANAR INTERMETAL DIELECTRIC USING A BARRIER LAYER
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09201581
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Filing Dt:
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11/30/1998
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Title:
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METHOD FOR FORMING A T-SHAPED PLUG HAVING INCREASED CONTACT AREA
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Patent #:
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Issue Dt:
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08/01/2000
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Application #:
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09206780
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Filing Dt:
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12/07/1998
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Title:
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METHOD FOR FABRICATING CONDUCTING LINES WITH A HIGH TOPOGRAPHY HEIGHT
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Patent #:
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Issue Dt:
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09/26/2000
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Application #:
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09206807
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Filing Dt:
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12/07/1998
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Title:
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METHOD OF FORMING STACKED CAPACITOR
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09209047
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Filing Dt:
|
12/09/1998
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Title:
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METHOD FOR FORMING A CROWN CAPACITOR
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Patent #:
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Issue Dt:
|
07/10/2001
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Application #:
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09241543
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Filing Dt:
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02/01/1999
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Title:
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METHOD FOR FORMING A BORDERLESS CONTACT
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09246919
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Filing Dt:
|
02/09/1999
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Title:
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METHOD TO REDUCE ASPECT RATIO OF DRAM PERIPHERAL CONTACT
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Patent #:
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|
Issue Dt:
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08/21/2001
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Application #:
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09247749
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Filing Dt:
|
02/09/1999
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Title:
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METHOD OF PLANARIZATION
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09250372
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Filing Dt:
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02/16/1999
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Title:
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METHOD OF FABRICATING A CAPACITOR ELECTRODE STRUCTURE IN A DYNAMIC RANDOM-ACCESS MEMORY DEVICE
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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09250594
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Filing Dt:
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02/16/1999
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Title:
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METHOD FOR FABRICATING A STACK CAPACITOR
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09250766
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Filing Dt:
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02/16/1999
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Title:
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SUB A2
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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09253322
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Filing Dt:
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02/19/1999
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Title:
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NEW SRAM CELL USING TWO SINGLE TRANSISTOR INVERTERS
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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09258083
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Filing Dt:
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02/25/1999
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Title:
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NEW SINGLE POLY EEPROM CELL STRUCTURE OPERATIONS AND ARRAY ARCHITECTURE
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09265357
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Filing Dt:
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03/10/1999
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Title:
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METHOD TO FABRICATE ELECTRODES FOR HIGH-K DIELECTRICS
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Patent #:
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Issue Dt:
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07/18/2000
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Application #:
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09275523
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Filing Dt:
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03/24/1999
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Title:
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NEW ELECTRON INJECTION METHOD FOR SUBSTRATE-HOT-ELECTRON PROGRAM AND ERASE VT TIGHTENING FOR ETOX CELL
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Patent #:
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Issue Dt:
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02/13/2001
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Application #:
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09280628
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Filing Dt:
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03/29/1999
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Title:
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METHOD FOR FABRICATING METAL INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
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08/21/2001
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Application #:
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09282052
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Filing Dt:
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03/29/1999
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Title:
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METHOD FOR PLANARIZING POLYSILICON LAYER
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09286014
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Filing Dt:
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04/05/1999
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Title:
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METHOD OF FABRICATING SHALLOW TRENCH ISOLATION STRUCTURE
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Patent #:
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Issue Dt:
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08/28/2001
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Application #:
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09286946
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Filing Dt:
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04/08/1999
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Title:
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TRANSISTOR AND LOGIC CIRCUIT OF THIN SILICON-ON-INSULATOR WAFERS BASED ON GATE INDUCED DRAIN LEAKAGE CURRENTS
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09287959
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Filing Dt:
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04/07/1999
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Title:
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METHOD FOR REDUCING CAPACITANCE DEPLETION DURING HEMISPHERICAL GRAIN POLYSILICON SYNTHESIS FOR DRAM
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Patent #:
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Issue Dt:
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02/08/2000
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Application #:
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09287998
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Filing Dt:
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04/07/1999
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Title:
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METHOD OF USING SILICON OXYNITRIDE TO IMPROVE FABRICATING OF DRAM CONTACTS AND LANDING PADS
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Patent #:
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Issue Dt:
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02/26/2002
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Application #:
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09290384
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Filing Dt:
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04/12/1999
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Title:
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HIGH SPEED BUILT-IN SELF-TEST CIRCUIT FOR DRAMS
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Patent #:
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Issue Dt:
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01/29/2002
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Application #:
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09293973
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Filing Dt:
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04/19/1999
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Title:
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DRAM CAPACITOR AND A METHOD OF FABRICATING THE SAME
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09293974
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Filing Dt:
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04/19/1999
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Title:
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METHOD OF FORMING A TUNGSTEN PLUG
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Patent #:
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Issue Dt:
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10/17/2000
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Application #:
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09295017
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Filing Dt:
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04/20/1999
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Title:
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NOR ARRAY ARCHITECTURE AND OPERATION METHODS FOR ETOX CELLS CAPABLE OF FULL EEPROM FUNCTIONS
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Patent #:
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Issue Dt:
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12/12/2000
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Application #:
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09299956
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Filing Dt:
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04/26/1999
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Title:
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STRUCTURE AND FABRICATING METHOD OF STACKED CAPACITOR
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Patent #:
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Issue Dt:
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01/23/2001
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Application #:
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09299963
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Filing Dt:
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04/26/1999
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Title:
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METHOD FOR MANUFACTURING STACKED CAPACITOR
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Patent #:
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Issue Dt:
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08/29/2000
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Application #:
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09301481
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Filing Dt:
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04/28/1999
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Title:
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METHOD FOR FORMING A HARD MASK OF HALF CRITICAL DIMENSION
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Patent #:
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Issue Dt:
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09/19/2000
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Application #:
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09301482
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Filing Dt:
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04/28/1999
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Title:
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METHOD OF FABRICATING DRAM WITH NOVEL LANDING PAD PROCESS
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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09303769
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Filing Dt:
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04/30/1999
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Title:
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ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT EMPLOYING MOSFETS HAVING DOUBLE ESD IMPLANTATIONS
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Patent #:
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Issue Dt:
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11/11/2003
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Application #:
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09303770
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Filing Dt:
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04/30/1999
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Title:
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BUILT-IN-SELF-TEST CIRCUIT FOR RAMBUS DIRECT RDRAM
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Patent #:
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Issue Dt:
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12/26/2000
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Application #:
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09306095
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Filing Dt:
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05/06/1999
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Title:
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METHOD FOR FABRICATING CAPACITOR
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Patent #:
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Issue Dt:
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05/22/2001
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Application #:
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09306097
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Filing Dt:
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05/06/1999
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Title:
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BONDING PAD STRUCTURE
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Patent #:
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Issue Dt:
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06/04/2002
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Application #:
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09306245
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Filing Dt:
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05/06/1999
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Publication #:
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Pub Dt:
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06/07/2001
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Title:
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METHOD FOR PLANARIZING OXIDE LAYER
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Patent #:
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Issue Dt:
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12/19/2000
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Application #:
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09306261
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Filing Dt:
|
05/06/1999
|
|
Title:
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METHOD OF MANUFACTURING DRAM CAPACITOR
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|
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Patent #:
|
|
Issue Dt:
|
04/03/2001
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Application #:
|
09306342
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Filing Dt:
|
05/06/1999
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|
Title:
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METHOD FOR MANUFACTURING METAL PLUG
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Patent #:
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Issue Dt:
|
12/26/2000
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Application #:
|
09306351
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Filing Dt:
|
05/06/1999
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Title:
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METHOD OF MANUFACTURING MASK READ-ONLY-MEMORY
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|
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Patent #:
|
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Issue Dt:
|
10/17/2000
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Application #:
|
09307760
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Filing Dt:
|
05/10/1999
|
|
Title:
|
HDP-CVD METHOD FOR SPACER FORMATION
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|
|
|
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Patent #:
|
|
Issue Dt:
|
07/17/2001
|
Application #:
|
09313169
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Filing Dt:
|
05/17/1999
|
|
Title:
|
MOVABLE MULTI-FUNCTION MAINTENANCE APPARATUS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/09/2000
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Application #:
|
09313170
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Filing Dt:
|
05/17/1999
|
|
Title:
|
ALIGNMENT-MARKER STRUCTURE AND METHOD OF FORMING THE SAME IN INTEGRATED CIRCUIT FABRICATION
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|
|
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Patent #:
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Issue Dt:
|
03/20/2001
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Application #:
|
09313521
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Filing Dt:
|
05/17/1999
|
|
Title:
|
METHOD OF MANUFACTURING BIT LINES IN MEMORY
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|
|
|
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Patent #:
|
|
Issue Dt:
|
04/17/2001
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Application #:
|
09314018
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Filing Dt:
|
05/19/1999
|
|
Title:
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METHOD OF MANUFACTURING A CONTACT FOR A CAPACITOR OF HIGH DENSITY DRAMS
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/22/2000
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Application #:
|
09314623
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Filing Dt:
|
05/19/1999
|
|
Title:
|
A VERTICAL THIN FILM TRANSISTOR
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|
|
|
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Patent #:
|
|
Issue Dt:
|
12/19/2000
|
Application #:
|
09317132
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Filing Dt:
|
05/24/1999
|
|
Title:
|
METHOD FOR FORMING A DRAM CAPACITOR
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|
|
|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
|
09317678
|
Filing Dt:
|
05/24/1999
|
|
Title:
|
USE OF ADENOSINE DEAMINASE INHIBITORS TO TREAT SYSTEMIC INFLAMMATORY RESPONSE SYNDROME
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|
|
|
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Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09326166
|
Filing Dt:
|
06/04/1999
|
|
Title:
|
DIGITALLY TUNABLE VOLTAGE REFERENCE USING A NEURON MOSFET
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/06/2001
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Application #:
|
09326390
|
Filing Dt:
|
06/04/1999
|
|
Title:
|
FABRICATION METHOD OF A TWIN-TUB CAPACITOR
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|
|
|
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Patent #:
|
|
Issue Dt:
|
03/20/2001
|
Application #:
|
09326391
|
Filing Dt:
|
06/04/1999
|
|
Title:
|
METHOD OF FABRICATING A CAPACITOR WITH A LOW-RESISTANCE ELECTRODE STRUCTURE IN INTEGRATED CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/29/2000
|
Application #:
|
09327093
|
Filing Dt:
|
06/04/1999
|
|
Title:
|
METHOD FOR MAKING A MOSFET WITH SELF-ALIGNED SOURCE AND DRAIN CONTACTS INCLUDING FORMING AN OXIDE LINER ON THE GATE, FORMING NITRIDE SPACERS ON THE LINER, ETCHING THE LINER, AND FORMING CONTACTS IN THE GAPS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/24/2000
|
Application #:
|
09328755
|
Filing Dt:
|
06/09/1999
|
|
Title:
|
METHOD FOR MANUFACTURING DRAM CAPACITOR
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09328978
|
Filing Dt:
|
06/09/1999
|
|
Publication #:
|
|
Pub Dt:
|
05/24/2001
| | | | |
|
Title:
|
METHOD FOR REDUCING CONTACT RESISTANCE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/17/2001
|
Application #:
|
09328980
|
Filing Dt:
|
06/09/1999
|
|
Title:
|
METHOD OF FABRICATING LOW VOLTAGE COEFFICIENT CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/12/2000
|
Application #:
|
09328981
|
Filing Dt:
|
06/09/1999
|
|
Title:
|
METHOD OF FABRICATING LANDING PAD
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09334080
|
Filing Dt:
|
06/16/1999
|
|
Title:
|
ETOX CELL HAVING BIPOLAR ELECTRON INJECTION FOR SUBSTRATE-HOT-ELECTRON PROGRAM
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09335547
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD FOR MANUFACTURING STACKED CAPACITOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09335553
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD OF FABRICATING COPPER DAMASCENE
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
09335632
|
Filing Dt:
|
06/18/1999
|
|
Publication #:
|
|
Pub Dt:
|
05/30/2002
| | | | |
|
Title:
|
METHOD OF FABRICATING GATE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09336044
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD OF FABRICATING A BONDING PAD STRUCTURE FOR IMPROVING THE BONDING PAD SURFACE QUALITY
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09336045
|
Filing Dt:
|
06/18/1999
|
|
Title:
|
METHOD OF PLANARIZING INTER-METAL DIELECTRIC LAYER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2001
|
Application #:
|
09342569
|
Filing Dt:
|
06/29/1999
|
|
Title:
|
A DUAL DAMASCENE PROCESS FOR CAPACITANCE FABRICATION OF DRAM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/21/2001
|
Application #:
|
09342570
|
Filing Dt:
|
06/29/1999
|
|
Title:
|
METHOD OF PROTECTING TUNGSTEN PLUG FROM CORRODING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/08/2000
|
Application #:
|
09342718
|
Filing Dt:
|
06/29/1999
|
|
Title:
|
Method Of Fabricating Capacitor Capable Of Maintaining The Height Of The Peripheral Area Of The Capacitor
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2000
|
Application #:
|
09346324
|
Filing Dt:
|
07/02/1999
|
|
Title:
|
METHOD FOR MAKING A DRAM CAPACITOR USING A ROTATED PHOTOLITHOGRAPHY MASK
|
|
