|
Total properties:
19
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/07/2000
|
Application #:
|
08940869
|
Filing Dt:
|
09/30/1997
|
|
Title:
|
METHOD AND APPARATUS FOR ENCODING A BINARY SIGNAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/01/2001
|
Application #:
|
09164864
|
Filing Dt:
|
10/01/1998
|
|
Title:
|
SYSTEM AND METHOD FOR GAIN COMPENSATION FOR THERMAL ASPERITY CORRECTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/22/2001
|
Application #:
|
09164867
|
Filing Dt:
|
10/01/1998
|
|
Title:
|
METHOD AND APPARATUS FOR REDUCING RINGING USING FEED FORWARD COMPENSATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09165182
|
Filing Dt:
|
10/01/1998
|
|
Title:
|
METHOD AND APPARTUS FOR ADAPTING THE BOOST OF A READ CHANNEL FILTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2002
|
Application #:
|
09250426
|
Filing Dt:
|
02/16/1999
|
|
Title:
|
MULTIPLEXED CODEC FOR AN ADSL SYSTEM
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/10/2001
|
Application #:
|
09323670
|
Filing Dt:
|
06/01/1999
|
|
Title:
|
DROOP-FREE QUASI-CONTINUOUS RECONSTRUCTION FILTER INTERFACE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/20/2001
|
Application #:
|
09354644
|
Filing Dt:
|
07/15/1999
|
|
Title:
|
INITIAL PHASE CONTROL OF AN OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
|
09354685
|
Filing Dt:
|
07/15/1999
|
|
Title:
|
DOUBLE-CLAMPED DELAY STAGE AND VOLTAGE CONTROLLED OSCILLATOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09383108
|
Filing Dt:
|
08/25/1999
|
|
Title:
|
LOW VOLTAGE BIPOLAR TRANSCONDUCTOR CIRCUIT WITH EXTENDED DYNAMIC RANGE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/08/2001
|
Application #:
|
09384850
|
Filing Dt:
|
08/27/1999
|
|
Title:
|
RATE 32/34 (D=0, G=9/I=9) MODULATION CODE WITH PARITY FOR A RECORDING CHANNEL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/06/2001
|
Application #:
|
09385190
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
VITERBI DETECTOR WITH PARTIAL ERASURE COMPENSATION FOR READ CHANNELS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/24/2001
|
Application #:
|
09386029
|
Filing Dt:
|
08/30/1999
|
|
Title:
|
ARCHITECTURE TO REDUCE ERRORS DUE TO METASTABILITY IN ANALOG TO DIGITAL CONVERTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/07/2001
|
Application #:
|
09387448
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
SUPPLY INDEPENDENT BIASING SCHEME
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2001
|
Application #:
|
09388036
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
DIFFERENTIAL CHARGE PUMP WITH REDUCED CHARGE-COUPLING EFFECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/19/2002
|
Application #:
|
09388037
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
ERROR SIGNAL CALCULATION FROM A VITERBI OUTPUT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/06/2001
|
Application #:
|
09388996
|
Filing Dt:
|
09/01/1999
|
|
Title:
|
MAGNITUDE AND GROUP DELAY SHAPING CIRCUIT IN CONTINUOUS-TIME READ CHANNEL FILTERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/18/2001
|
Application #:
|
09408016
|
Filing Dt:
|
09/29/1999
|
|
Title:
|
DIGITAL-TO-ANALOG CONVERTER USING WEIGHTS STORED IN A WEIGHT TABLE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2001
|
Application #:
|
09411342
|
Filing Dt:
|
10/01/1999
|
|
Title:
|
DIGITALLY CALIBRATED BANDGAP REFERENCE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/04/2003
|
Application #:
|
09689872
|
Filing Dt:
|
10/13/2000
|
|
Title:
|
FGL-2 KNOCKOUT MICE
|
|
