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Patent Assignment Details
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Reel/Frame:011209/0306   Pages: 2
Recorded: 10/10/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
02/18/2003
Application #:
09684335
Filing Dt:
10/10/2000
Title:
WIRING DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Assignor
1
Exec Dt:
10/02/2000
Assignee
1
7-1, SHIBA 5-CHOME, MINATO-KU
TOKYO, JAPAN
Correspondence name and address
FOLEY & LARDNER
DAVID A. BLUMENTHAL
WASHINGTON HARBOUR
3000 K STREET, NW SUITE 500
WASHINGTON D.C 20007-5109

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