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Patent Assignment Details
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Reel/Frame:011503/0357   Pages: 7
Recorded: 11/13/2000
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
12/14/2004
Application #:
09652550
Filing Dt:
08/31/2000
Title:
METHODS OF FORMING AN ISOLATION TRENCH IN A SEMICONDUCTOR, METHODS OF FORMING AN ISOLATION TRENCH IN A SURFACE OF A SILICON WAFER, METHODS OF FORMING AN ISOLATION TRENCH-ISOLATED TRANSISTOR, TRENCH-ISOLATED TRANSISTOR, TRENCH ISOLATION STRUCTURES FORMED IN A SEMICO
Assignors
1
Exec Dt:
10/31/2000
2
Exec Dt:
10/31/2000
3
Exec Dt:
10/31/2000
Assignees
1
8000 SOUTH FEDERAL WAY
BOISE, IDAHO 83716
2
302-2, HIRANO-CHO, NISHIWAKI-SHI
HYOGO, JAPAN 677-0
Correspondence name and address
WELLS, ST. JOHN, ROBERTS, GREGORY,ET AL.
FREDERICK M. FLIEGEL, PH.D.
601 WEST FIRST AVE., STE. 1300
SPOKANE, WA 99201-3828

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