Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 011562/0778 | |
| Pages: | 2 |
| | Recorded: | 02/22/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/13/2003
|
Application #:
|
09789490
|
Filing Dt:
|
02/22/2001
|
|
Publication #:
|
|
Pub Dt:
|
01/10/2002
| | | | |
|
Title:
|
METHOD OF DESIGNING A LAYOUT OF AN LSI CHIP, AND A COMPUTER PRODUCT
|
|
|
Assignee
|
|
|
|
|
| NAKAHARA-KU, KAWASAKI-SHI |
| 1-1, KAMIKODANAKA 4-CHOME |
| KANAGAWA 211-8588, JAPAN |
|
|
Correspondence name and address
|
| |
STAAS & HALSEY, LLP
|
| |
H. J. STAAS
|
| |
700 ELEVENTH STREET, N.W., SUITE 500
|
| |
WASHINGTON, DC 20001
|
Search Results as of:
04/26/2024 12:33 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
