Patent Assignment Details
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| Reel/Frame: | 011670/0485 | |
| Pages: | 2 |
| | Recorded: | 03/23/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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03/30/2004
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Application #:
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09713517
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Filing Dt:
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11/14/2000
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Title:
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METHOD FOR REDUCING STORED PATTERNS FOR IC TEST BY EMBEDDING BUILT-IN-SELF-TEST CIRCUITRY FOR CHIP LOGIC INTO A SCAN TEST ACCESS PORT
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Assignee
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| LEGAL DEPARTMENT, 51U-PD, INTELLECTUAL PROPERTY ADMINISTRATION |
| P.O. BOX 58043 |
| SANTA CLARA, CALIFORNIA 95052 |
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Correspondence name and address
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AGILENT TECHNOLOGIES, INC.
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PATRICIA FILSINGER
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815 SW 14TH STREET
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LOVELAND, CO 80537
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