Patent Assignment Details
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| Reel/Frame: | 012142/0026 | |
| Pages: | 3 |
| | Recorded: | 08/29/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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02/01/2005
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Application #:
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09943779
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Filing Dt:
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08/29/2001
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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VARIABLE DELAY CIRCUIT AND METHOD, AND DELAY LOCKED LOOP, MEMORY DEVICE AND COMPUTER SYSTEM USING SAME
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Assignee
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| 8000 SOUTH FEDERAL WAY |
| BOISE, IDAHO 83716 |
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Correspondence name and address
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EDWARD W. BULCHIS
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DORSEY & WHITNEY LLP
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SUITE 3400
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1420 FIFTH AVENUE
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SEATTLE, WA 98101
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