Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 012260/0720 | |
| Pages: | 4 |
| | Recorded: | 10/03/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/10/2002
|
Application #:
|
09913010
|
Filing Dt:
|
10/03/2001
|
|
Publication #:
|
|
Pub Dt:
|
09/26/2002
| | | | |
|
Title:
|
SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE ARCHITECTURE
|
|
|
Assignee
|
|
|
|
|
| 1006, OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571-8 |
|
|
Correspondence name and address
|
| |
SNELL & WILMER, LLP
|
| |
MICHAEL K. KELLY
|
| |
ONE ARIZONA CENTER
|
| |
400 E. VAN BUREN STREET
|
| |
PHOENIX, AZ 85004-2202
|
Search Results as of:
04/19/2024 05:05 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
