Patent Assignment Details
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| Reel/Frame: | 012390/0405 | |
| Pages: | 3 |
| | Recorded: | 12/07/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/05/2005
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Application #:
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10020565
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Filing Dt:
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12/07/2001
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Publication #:
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Pub Dt:
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06/12/2003
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Title:
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MEMORY CONTROLLER AND METHOD USING READ AND WRITE QUEUES AND AN ORDERRING QUEUE FOR DISPATCHING READ AND WRITE MEMORY REQUESTS OUT OF ORDER TO REDUCE MEMORY LATENCY
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Assignee
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| 901 SAN ANTONIO ROAD |
| PALO ALTO, CALIFORNIA 94303 |
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Correspondence name and address
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WILLIAM L. PARADICE III
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511 LINDEN STREET, #B
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SAN FANCISCO, CA 94102
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