Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 012422/0592 | |
| Pages: | 3 |
| | Recorded: | 12/28/2001 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10028320
|
Filing Dt:
|
12/28/2001
|
|
Publication #:
|
|
Pub Dt:
|
12/26/2002
| | | | |
|
Title:
|
Method of performing bit modeling and circuit that uses this method
|
|
|
Assignee
|
|
|
|
|
| CHIYODA-KU |
| 2-3, MARUNOUCHI 2-CHOME |
| TOKYO 100-8310, JAPAN |
|
|
Correspondence name and address
|
| |
BURNS, DOANE, SWECKER & MATHIS, L.L.P.
|
| |
PLATON N. MANDROS
|
| |
P.O. BOX 1404
|
| |
ALEXANDRIA, VIRGINIA 22313-1404
|
Search Results as of:
05/01/2024 07:55 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
