Patent Assignment Details
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| Reel/Frame: | 012429/0932 | |
| Pages: | 3 |
| | Recorded: | 01/02/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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06/14/2005
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Application #:
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09945247
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Filing Dt:
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08/31/2001
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Publication #:
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Pub Dt:
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04/18/2002
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Title:
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METHOD FOR FABRICATION OF FIELD-EFFECT TRANSISTOR TO REDUCE DEFECTS AT MOS INTERFACES FORMED AT LOW TEMPERATURE
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Assignee
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| 4-1, NISHI-SHINJUKU 2-CHOME, SHINJUKU-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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HARNESS, DICKEY & PIERCE, P.L.C.
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G. GREGORY SCHIVLEY/BRYANT E. WADE
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P.O. BOX 828
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BLOOMFIELD HILLS, MI 48303
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