Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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Reel/Frame: | 012442/0365 | |
| Pages: | 5 |
| | Recorded: | 01/09/2002 | | |
Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF CONVEYING PARTY THAT WAS PREVIOUSLY RECORDED ON REEL 012201, FRAME 0748. |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09960399
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Filing Dt:
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09/24/2001
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Publication #:
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Pub Dt:
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12/26/2002
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Title:
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A SEMICONDUCTOR INTEGRATED CIRCUIT AND FABRICATION PROCESS HAVING COMPENSATED STRUCTURES TO REDUCE MANUFACTURING DEFECTS
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Assignee
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1-1, KAMIKODANAKA 4-CHOME, NAKAHARA-KU |
KAWASAKI-SHI, KANAGAWA, 211-8588, JAPAN |
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Correspondence name and address
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ARMSTRONG, WESTERMAN & HATTORI, LLP
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MEL R. QUINTOS
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1725 K STREET, N.W.
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SUITE 1000
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WASHINGTON, DC 20006
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