Patent Assignment Details
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| Reel/Frame: | 012481/0947 | |
| Pages: | 4 |
| | Recorded: | 01/15/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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09916598
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Filing Dt:
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07/26/2001
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Publication #:
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Pub Dt:
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01/30/2003
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Title:
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Cache coherent split transaction memory bus architecture and protocol for a multi processor chip device
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Assignee
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| INTELLECTUAL PROPERTY ADMINISTRATION |
| P.O BOX 272400 |
| FORT COLLINS, COLORADO 80527 |
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Correspondence name and address
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HEWLETT-PACKARD COMPANY
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RECORDS MANAGER
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ANN JESUS
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1501 PAGE MILL RD M/S 4U-10
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PALO ALTO, CA 94304
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