Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 012641/0086 | |
| Pages: | 5 |
| | Recorded: | 02/20/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
4
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Patent #:
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Issue Dt:
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04/28/1987
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Application #:
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06448002
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Filing Dt:
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12/08/1982
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Title:
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PROGRAMMED LOGIC ARRAY WITH TWO-LEVEL CONTROL TIMING
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Patent #:
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Issue Dt:
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05/26/1987
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Application #:
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06593099
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Filing Dt:
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03/26/1984
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Title:
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CHAIN LOGIC SCHEME FOR PROGRAMMED LOGIC ARRAY
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Patent #:
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Issue Dt:
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09/29/1987
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Application #:
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06888796
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Filing Dt:
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07/23/1986
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Title:
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CMOS PROGRAMMABLE LOGIC ARRAY
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Patent #:
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Issue Dt:
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06/11/2002
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Application #:
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09400029
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Filing Dt:
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09/21/1999
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Title:
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INTEGRATED CIRCUIT WITH STANDARD CELL LOGIC AND SPARE GATES
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Assignee
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| 5555 NE MOORE COURT |
| HILLSBORO, OREGON 97124 |
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Correspondence name and address
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LATTICE SEMICONDUCTOR CORP.
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MARK L. BECKER
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5555 NE MOORE COURT
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HILLSBORO, OR 97124
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