Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 012643/0710 | |
| Pages: | 5 |
| | Recorded: | 02/20/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
5
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Patent #:
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Issue Dt:
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11/26/2002
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Application #:
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09864276
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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SIGNAL DISTRIBUTION SCHEME IN FIELD PROGRAMMABLE GATE ARRAY (FPGA) OR FIELD PROGRAMMABLE SYSTEM CHIP (FPSC) INCLUDING CYCLE STEALING UNITS
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Patent #:
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Issue Dt:
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11/19/2002
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Application #:
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09864277
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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MULTI-MASTER MULTI-SLAVE SYSTEM BUS IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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Patent #:
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Issue Dt:
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10/29/2002
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Application #:
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09864284
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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DOUBLE DATA RATE INPUT AND OUTPUT IN A PROGRAMMABLE LOGIC DEVICE
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09864289
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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01/10/2002
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Title:
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MULTI-FUNCTIONAL I/O BUFFERS IN A FIELD PROGRAMMABLE GATE ARRAY (FPGA)
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Patent #:
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Issue Dt:
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08/03/2004
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Application #:
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09864290
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Filing Dt:
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05/25/2001
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Publication #:
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Pub Dt:
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01/24/2002
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Title:
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FIELD PROGRAMMABLE GATE ARRAY (FPGA) BIT STREAM FORMAT
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Assignee
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| 5555 NE MOORE COURT |
| HILLSBORO, OREGON 97124 |
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Correspondence name and address
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LATTICE SEMICONDUCTOR CORP.
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MARK BECKER
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5555 NE MOORE COURT
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HILLSBORO, OR 97124
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