Patent Assignment Details
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| Reel/Frame: | 012663/0102 | |
| Pages: | 3 |
| | Recorded: | 03/01/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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04/27/2004
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Application #:
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10085009
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Filing Dt:
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03/01/2002
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Publication #:
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Pub Dt:
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09/12/2002
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Title:
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WIRING METHOD IN LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND FUNCTIONAL MACRO
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Assignee
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| KADOMA-SHI |
| 1006, OAZA KADOMA |
| OSAKA 571-8501, JAPAN |
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Correspondence name and address
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MCDERMOTT, WILL & EMERY
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MICHAEL E. FOGARTY
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600 13TH ST., N.W.
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WASHINGTON, D.C. 20005
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