Patent Assignment Details
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Reel/Frame: | 013102/0817 | |
| Pages: | 2 |
| | Recorded: | 07/10/2002 | | |
Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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10/26/2004
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Application #:
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10192989
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Filing Dt:
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07/10/2002
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Publication #:
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Pub Dt:
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01/15/2004
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Title:
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INTEGRATED CIRCUIT DESIGN FLOW WITH CAPACITIVE MARGIN
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Assignee
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1551 MCCARTHY BOULEVARD |
MILPITAS, CALIFORNIA 95035 |
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Correspondence name and address
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LSI LOGIC CORP.
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ERIC J. WHITESELL
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1551 MCCARTHY BLVD.
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MILPITAS, CA 95035
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