Patent Assignment Details
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| Reel/Frame: | 013612/0449 | |
| Pages: | 2 |
| | Recorded: | 12/23/2002 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10325964
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Filing Dt:
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12/23/2002
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Publication #:
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Pub Dt:
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09/18/2003
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Title:
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INTEGRATED CIRCUIT LAYOUT METHOD AND PROGRAM FOR MITIGATING EFFECT DUE TO VOLTAGE DROP OF POWER SUPPLY WIRING
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Assignee
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| 1-1 KAMIKODANAKA, 4-CHOME, NAKAHARA-KU, |
| KAWASAKI-SHI, KANAGAWA 211-8588, JAPAN |
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Correspondence name and address
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STAAS & HALSEY LLP
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H.J. STAAS
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700 ELEVENTH STREET, N.W.
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SUITE 500
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WASHINGTON, NY 20001
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