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Patent Assignment Details
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Reel/Frame:013698/0106   Pages: 3
Recorded: 01/24/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 9
1
Patent #:
Issue Dt:
08/15/2000
Application #:
09075531
Filing Dt:
05/11/1998
Title:
DELAY CIRCUIT DEVICE HAVING A REDUCED CURRENT CONSUMPTION
2
Patent #:
Issue Dt:
11/14/2000
Application #:
09106266
Filing Dt:
06/29/1998
Title:
REFERENCE VOLTAGE GENERATING CIRCUIT OF GENERATING A PLURALITY OF REFERENCE VOLTAGES
3
Patent #:
Issue Dt:
06/14/2005
Application #:
09570389
Filing Dt:
05/12/2000
Title:
DEVICE FOR SIMULATING CIRCUITS, METHOD FOR SIMULATING THE SAME, AND RECORDING MEDIUM
4
Patent #:
Issue Dt:
11/05/2002
Application #:
09588189
Filing Dt:
06/07/2000
Title:
CHIP-SIZE INTEGRATED CIRCUIT PACKAGE HAVING SLITS FORMED IN AN INSULATOR TAPE
5
Patent #:
Issue Dt:
01/07/2003
Application #:
09633133
Filing Dt:
08/04/2000
Title:
SEMICONDUCTOR MEMORY APPARATUS THAT CAN PREVENT WRITE LEVEL OF DATA TO MEMORY CELL FROM DROPPING AND IMPROVE SENSE SPEED AT NEXT CYCLE
6
Patent #:
Issue Dt:
07/30/2002
Application #:
09676781
Filing Dt:
10/02/2000
Title:
SEMICONDUCTOR MEMORY AND METHOD FOR FABRICATING THE SAME
7
Patent #:
Issue Dt:
03/11/2003
Application #:
09811529
Filing Dt:
03/20/2001
Publication #:
Pub Dt:
10/04/2001
Title:
SEMICONDUCTOR MEMORY PRODUCTION SYSTEM AND SEMICONDUCTOR MEMORY PRODUCTION METHOD
8
Patent #:
NONE
Issue Dt:
Application #:
10044963
Filing Dt:
01/15/2002
Publication #:
Pub Dt:
05/16/2002
Title:
Failure analyzing device for semiconductors
9
Patent #:
Issue Dt:
05/30/2006
Application #:
10044964
Filing Dt:
01/15/2002
Publication #:
Pub Dt:
05/16/2002
Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
Assignor
1
Exec Dt:
01/10/2003
Assignee
1
1753 SHIMONUMABE, NAKAHARA-KU
KAWASAKI, KANAGAWA 211-8668, JAPAN
Correspondence name and address
FOLEY & LARDNER
DAVID A. BLUMENTHAL
WASHINGTON HARBOUR
3000 K STREET, N.W., SUITE 500
WASHINGTON, D.C. 20007-5143

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