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Patent Assignment Details
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Reel/Frame:013824/0055   Pages: 11
Recorded: 07/23/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
02/15/2005
Application #:
10463643
Filing Dt:
06/17/2003
Title:
METHOD OF FABRICATING A PLANAR STRUCTURE CHARGE TRAPPING MEMORY CELL ARRAY WITH RECTANGULAR GATES AND REDUCED BIT LINE RESISTANCE
Assignors
1
Exec Dt:
02/26/2002
2
Exec Dt:
04/14/2003
3
Exec Dt:
04/10/2003
4
Exec Dt:
03/24/2003
5
Exec Dt:
05/08/2003
6
Exec Dt:
03/28/2003
7
Exec Dt:
04/02/2003
8
Exec Dt:
04/10/2003
9
Exec Dt:
04/10/2003
Assignee
1
ONE AMD PLACE
P.O. BOX 3453
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
RENNER OTTO BOISSELLE, ET AL.
MARK D. SARALINO
1621 EUCLID AVENUE
19TH FLOOR
CLEVELAND, OH 44115

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