Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 013904/0981 | |
| Pages: | 2 |
| | Recorded: | 03/31/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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03/22/2005
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Application #:
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09570863
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Filing Dt:
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05/12/2000
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Title:
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FAILURE ANALYSIS SYSTEM OF SEMICONDUCTOR MEMORY DEVICE
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10226258
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Filing Dt:
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08/23/2002
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Publication #:
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Pub Dt:
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12/19/2002
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Title:
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Package having terminated plating layer and its manufacturing method
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Patent #:
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Issue Dt:
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06/03/2003
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Application #:
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10255700
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Filing Dt:
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09/27/2002
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Publication #:
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Pub Dt:
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02/06/2003
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Title:
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METHOD OF MEASURING OPTICAL ABERRATION
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Patent #:
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Issue Dt:
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02/14/2006
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Application #:
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10284191
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Filing Dt:
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10/31/2002
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Publication #:
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Pub Dt:
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05/08/2003
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Title:
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CLEANING METHOD, METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND CLEANING SOLUTION
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10303715
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Filing Dt:
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11/26/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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Semiconductor device and method of manufacturing the same
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Patent #:
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Issue Dt:
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07/12/2005
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Application #:
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10307404
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Filing Dt:
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12/02/2002
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Publication #:
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Pub Dt:
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06/05/2003
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Title:
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ALIGNMENT PATTERN FOR A SEMICONDUCTOR DEVICE MANUFACTURING PROCESS
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Assignee
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| 1753 SHIMONUMABE, NAKAHARA-KU, KAWASAKI |
| KANAGAWA 211-8668, JAPAN |
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Correspondence name and address
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YOUNG & THOMPSON
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BENOIT CASTEL
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SECOND FLOOR
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745 SOUTH 23RD STREET
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ARLINGTON, VA 22202
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