Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
| Reel/Frame: | 014142/0115 | |
| Pages: | 3 |
| | Recorded: | 06/04/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
|
|
Total properties:
1
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
10453621
|
Filing Dt:
|
06/04/2003
|
|
Publication #:
|
|
Pub Dt:
|
12/11/2003
| | | | |
|
Title:
|
METHOD OF GENERATING TIMING CONSTRAINT MODEL OF LOGIC CIRCUIT, PROGRAM FOR GENERATING TIMING CONSTRAINT MODEL OF LOGIC CIRCUIT, AND TIMING-DRIVEN LAYOUT METHOD OF USING THE TIMING CONSTRAINT MODEL
|
|
|
Assignee
|
|
|
|
|
| 1-1, KAMIKODANAKA, 4-CHOME |
| NAKAHARA-KU, KAWASAKI-SHI |
| KANAGAWA 211-8588, JAPAN |
|
|
Correspondence name and address
|
| |
STAAS & HALSEY LLP
|
| |
ATTN: H. J. STAAS
|
| |
700 ELEVENTH STREET, N.W.
|
| |
SUITE 500
|
| |
WASHINGTON, D.C. 20001
|
Search Results as of:
05/05/2024 02:39 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
