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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:014147/0126   Pages: 4
Recorded: 11/20/2003
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 6
1
Patent #:
Issue Dt:
08/09/2005
Application #:
10248841
Filing Dt:
02/24/2003
Publication #:
Pub Dt:
08/26/2004
Title:
PROCESS TO SUPPRESS LITHOGRAPHY AT A WAFER EDGE
2
Patent #:
Issue Dt:
01/13/2015
Application #:
10386974
Filing Dt:
03/12/2003
Publication #:
Pub Dt:
09/16/2004
Title:
Multiple delay locked loop integration system and method
3
Patent #:
Issue Dt:
05/10/2005
Application #:
10397761
Filing Dt:
03/26/2003
Publication #:
Pub Dt:
09/30/2004
Title:
TRENCH ISOLATION EMPLOYING A DOPED OXIDE TRENCH FILL
4
Patent #:
Issue Dt:
08/31/2004
Application #:
10410496
Filing Dt:
04/09/2003
Title:
IN SITU METAL BARRIER DEPOSITION FOR SPUTTER ETCH ON AN INTERCONNECT STRUCTURE
5
Patent #:
NONE
Issue Dt:
Application #:
10411279
Filing Dt:
04/11/2003
Publication #:
Pub Dt:
10/14/2004
Title:
System and method for performing a metal layer RIE process
6
Patent #:
Issue Dt:
12/13/2005
Application #:
10600034
Filing Dt:
06/20/2003
Publication #:
Pub Dt:
12/23/2004
Title:
SELF-ALIGNED MASK TO REDUCE CELL LAYOUT AREA
Assignor
1
Exec Dt:
11/19/2003
Assignee
1
ST. MARTIN-STR. 53
81669 MUNICH, GERMANY
Correspondence name and address
INFINEON TECHNOLOGIES NORTH ET AL
STANTON C. BRADEN, ESQ.
170 WOOD AVENUE SOUTH
ISELIN, NJ 08830

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