Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Reel/Frame: | 014155/0089 | |
| Pages: | 4 |
| | Recorded: | 06/10/2003 | | |
Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S ADDRESS PREVIOUSLY RECORDED ON REEL 013451, FRAME 0495. ASSIGNOR HEREBY CONFIRMS THE ASSIGNMENT OF THE ENTIRE INTEREST. |
|
Total properties:
1
|
|
Patent #:
|
|
Issue Dt:
|
11/02/2004
|
Application #:
|
10285540
|
Filing Dt:
|
11/01/2002
|
Publication #:
|
|
Pub Dt:
|
05/01/2003
| | | | |
Title:
|
SEMICONDUCTOR MEMORY HAVING STORAGE CELLS STORING MULTIPLE BITS AND A METHOD OF MANUFACTURING THE SAME
|
|
Assignee
|
|
|
17-6, SHIN-YOKOHAMA 3-CHOME, KOUHOKU-KU, YOKOHAMA |
KANAGAWA, JAPAN 222-8580 |
|
Correspondence name and address
|
|
BIRCH, STEWART, KOLASCH & BIRCH, LLP
|
|
MICHAEL K. MUTTER
|
|
P.O. BOX 747
|
|
FALLS CHURCH, VA 22040-0747
|
Search Results as of:
05/06/2024 09:12 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|