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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	014515/0249			Pages:	4
		Recorded:	04/14/2004
Conveyance:	ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).

Total properties: 10

Patent #:	6699750	Issue Dt:	03/02/2004	Application #:	09145623	Filing Dt:	09/02/1998
Title:	VERTICAL DEVICE FORMED ADJACENT TO A WORDLINE SIDEWALL AND METHOD FOR SEMICONDUCTOR CHIPS

Patent #:	6559002	Issue Dt:	05/06/2003	Application #:	10032041	Filing Dt:	12/31/2001
Title:	ROUGH OXIDE HARD MASK FOR DT SURFACE AREA ENHANCEMENT FOR DT DRAM

Patent #:	6914844	Issue Dt:	07/05/2005	Application #:	10378472	Filing Dt:	03/03/2003
Publication #:	US20040174762	Pub Dt:	09/09/2004
Title:	DEEP POWER DOWN SWITCH FOR MEMORY DEVICE

Patent #:	6889154	Issue Dt:	05/03/2005	Application #:	10402033	Filing Dt:	03/28/2003
Publication #:	US20040032683	Pub Dt:	02/19/2004
Title:	METHOD AND APPARATUS FOR CALIBRATING DATA-DEPENDENT NOISE PREDICTION

Patent #:	7522678	Issue Dt:	04/21/2009	Application #:	10402654	Filing Dt:	03/28/2003
Publication #:	US20040037373	Pub Dt:	02/26/2004
Title:	METHOD AND APPARATUS FOR A DATA-DEPENDENT NOISE PREDICTIVE VITERBI

Patent #:	6940773	Issue Dt:	09/06/2005	Application #:	10404561	Filing Dt:	04/02/2003
Publication #:	US20040196718	Pub Dt:	10/07/2004
Title:	METHOD AND SYSTEM FOR MANUFACTURING DRAMS WITH REDUCED SELF-REFRESH CURRENT REQUIREMENTS

Patent #:	7137049	Issue Dt:	11/14/2006	Application #:	10425224	Filing Dt:	04/29/2003
Publication #:	US20040221210	Pub Dt:	11/04/2004
Title:	METHOD AND APPARATUS FOR MASKING KNOWN FAILS DURING MEMORY TESTS READOUTS

Patent #:	6870211	Issue Dt:	03/22/2005	Application #:	10605590	Filing Dt:	10/10/2003
Publication #:	US20050077562	Pub Dt:	04/14/2005
Title:	SELF-ALIGNED ARRAY CONTACT FOR MEMORY CELLS

Patent #:	6956409	Issue Dt:	10/18/2005	Application #:	10651281	Filing Dt:	08/28/2003
Publication #:	US20050046451	Pub Dt:	03/03/2005
Title:	REFERENCE VOLTAGE DETECTOR FOR POWER-ON SEQUENCE IN A MEMORY

Patent #:	NONE	Issue Dt:		Application #:	10653741	Filing Dt:	09/02/2003
Publication #:	US20050045918	Pub Dt:	03/03/2005
Title:	Hybrid vertical twisted bitline architecture

Assignor

Exec Dt:

04/14/2004

Assignee

ST.-MARTIN-STR. 53

81669 MUNCHEN, GERMANY

Correspondence name and address
	INFINEON TECHNOLOGIES NORTH AMERICA CORP
	GUDRUN VOELKER
	IFNA CPC IC
	3000 CENTREGREEN WAY
	CARY, NC 27513

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