Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014557/0982 | |
| Pages: | 3 |
| | Recorded: | 09/26/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
3
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Patent #:
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Issue Dt:
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08/17/2004
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Application #:
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09886267
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Filing Dt:
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06/22/2001
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Publication #:
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Pub Dt:
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10/18/2001
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Title:
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DATA PROCESSOR CAPABLE OF EXECUTING AN INSTRUCTION THAT MAKES A CACHE MEMORY INEFECTIVE
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Patent #:
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Issue Dt:
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06/08/2004
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Application #:
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10172290
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Filing Dt:
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06/13/2002
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Publication #:
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Pub Dt:
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03/06/2003
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Title:
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SINGLE-CHIP MICROCOMPUTER WITH INTEGRAL CLOCK GENERATING UNIT PROVIDING CLOCK SIGNALS TO CPU, INTERNAL CIRCUIT MODULES AND SYNCHRONOUSLY CONTROLLING EXTERNAL DYNAMIC MEMORY
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Patent #:
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Issue Dt:
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05/11/2004
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Application #:
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10264618
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Filing Dt:
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10/04/2002
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Publication #:
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Pub Dt:
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12/18/2003
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Title:
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SINGLE-CHIP MICROCOMPUTER WITH HIERARCHICAL INTERNAL BUS STRUCTURE HAVING DATA AND ADDRESS SIGNAL LINES COUPLING CPU WITH OTHER PROCESSING ELEMENTS
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Assignee
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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Correspondence name and address
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ANTONELLI, TERRY, STOUT & KRAUS
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1300 N. SEVENTEENTH ST.
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SUITE 1800
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ARLINGTON, VA 22209
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