Patent Assignment Details
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| Reel/Frame: | 014710/0165 | |
| Pages: | 4 |
| | Recorded: | 11/19/2003 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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09/14/2010
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Application #:
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10612033
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Filing Dt:
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07/03/2003
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Publication #:
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Pub Dt:
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05/27/2004
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Title:
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SEMICONDUCTOR MEMORY PREVENTING AN ELECTRIC SHORT CIRCUIT BETWEEN A WORD LINE AND A SEMICONDUCTOR SUBSTRATE, AND MANUFACTURING METHOD FOR THE SEMICONDUCTOR MEMORY
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Assignee
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| 1-1, SHIBAURA 1-CHOME, MINATO-KU |
| TOKYO, JAPAN |
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Correspondence name and address
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FINNEGAN, HENDERSON, FARABOW ET.AL.
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ERNEST F. CHAPMAN
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1300 I STREET, N.W.
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WASHINGTON, D.C. 20005-3315
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