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Total properties:
16
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Patent #:
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Issue Dt:
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02/02/1999
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Application #:
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08772131
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Filing Dt:
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12/20/1996
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Title:
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BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING
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Patent #:
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Issue Dt:
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10/13/1998
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Application #:
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08799074
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Filing Dt:
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02/11/1997
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Title:
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HIGH-VOLTAGE CMOS LEVEL SHIFTER
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Patent #:
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Issue Dt:
|
09/01/1998
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Application #:
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08808237
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Filing Dt:
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02/28/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR
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Patent #:
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Issue Dt:
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06/15/1999
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Application #:
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08940674
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Filing Dt:
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09/30/1997
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Title:
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A DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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Patent #:
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Issue Dt:
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12/22/1998
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Application #:
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08944904
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Filing Dt:
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10/06/1997
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Title:
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HIGH VOLTAGE NMOS PASS GATE FOR INTEGRATED CIRCUIT WITH HIGH VOLTAGE GENERATOR AND FLASH NON-VOLATILE MEMORY DEVICE HAVING THE PASS GATE
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09063688
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Filing Dt:
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04/21/1998
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Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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|
|
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Patent #:
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Issue Dt:
|
03/07/2000
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Application #:
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09159023
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Filing Dt:
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09/23/1998
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Title:
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METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
|
11/30/1999
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Application #:
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09159142
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Filing Dt:
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09/23/1998
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Title:
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SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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09159342
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Filing Dt:
|
09/23/1998
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Title:
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MEMORY ADDRESS DECODING CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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|
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Patent #:
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|
Issue Dt:
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08/14/2001
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Application #:
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09159489
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Filing Dt:
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09/23/1998
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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|
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Patent #:
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|
Issue Dt:
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11/30/1999
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Application #:
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09175646
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Filing Dt:
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10/20/1998
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Title:
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SCHEME FOR PAGE ERASE AND ERASE VERIFY IN A NON -VOLATILE MEMORY ARRAY
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Patent #:
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Issue Dt:
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11/02/1999
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Application #:
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09175647
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Filing Dt:
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10/20/1998
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Title:
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BIT LINE BIASING METHOD TO ELIMATE PROGRAM DISTURBANCE IN A NON-VOLATILE MEMORY DEVICE AND MEMORY DEVICE EMPLOYING THE SAME
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|
|
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Patent #:
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|
Issue Dt:
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11/07/2000
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Application #:
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09283308
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Filing Dt:
|
03/31/1999
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Title:
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BARRIER LAYER DECREASES NITROGEN CONTAMINATION OF PERIPHERAL GATE REGIONS DURING TUNNEL OXIDE NITRIDATION
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|
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Patent #:
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|
Issue Dt:
|
07/24/2001
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Application #:
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09410512
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Filing Dt:
|
09/30/1999
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|
Title:
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DUAL SOURCE SIDE POLYSILICON SELECT GATE STRUCTURE AND PROGRAMMING METHOD UTILIZING SINGLE TUNNEL OXIDE FOR NAND ARRAY FLASH MEMORY
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|
|
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Patent #:
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|
Issue Dt:
|
10/14/2003
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Application #:
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09892431
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Filing Dt:
|
06/26/2001
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Publication #:
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Pub Dt:
|
01/24/2002
| | | | |
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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|
|
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09893247
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Filing Dt:
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06/26/2001
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Publication #:
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Pub Dt:
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12/13/2001
| | | | |
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Title:
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BANK SELECTOR CIRCUIT FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
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|
