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Total properties:
20
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426205
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE IN A MONOS DEVICE USING A DUAL LAYER HARD MASK
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Patent #:
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Issue Dt:
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04/17/2001
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Application #:
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09426239
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Filing Dt:
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10/25/1999
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Title:
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METHOD TO GENERATE A MONOS TYPE FLASH CELL USING POLYCRYSTALLINE SILICON AS AN ONO TOP LAYER
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09426430
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Filing Dt:
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10/25/1999
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Title:
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METHOD OF FABRICATING AN ONO DIELECTRIC BY NITRIDATION FOR MNOS MEMORY CELLS
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Patent #:
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Issue Dt:
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07/24/2001
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Application #:
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09426672
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Filing Dt:
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10/25/1999
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Title:
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HIGH TEMPERATURE OXIDE DEPOSITION PROCESS FOR FABRICATING AN ONO FLOATING-GATE ELECTRODE IN A TWO BIT EEPROM DEVICE
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Patent #:
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Issue Dt:
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09/12/2000
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Application #:
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09427402
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Filing Dt:
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10/25/1999
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Title:
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INTEGRATED METHOD BY USING HIGH TEMPERATURE OXIDE FOR TOP OXIDE AND PERIPHERY GATE OXIDE
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Patent #:
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Issue Dt:
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06/05/2001
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Application #:
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09427404
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Filing Dt:
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10/25/1999
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Title:
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PROCESS FOR FABRICATING A BIT-LINE USING BURIED DIFFUSION ISOLATION
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09492353
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Filing Dt:
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01/27/2000
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Title:
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Two bit flash cell with two floating gate regions
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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09532347
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Filing Dt:
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03/21/2000
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE USING HIGH TEMPERATURE DESCUM
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Patent #:
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Issue Dt:
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08/13/2002
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Application #:
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09535255
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Filing Dt:
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03/23/2000
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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Patent #:
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Issue Dt:
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10/08/2002
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Application #:
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09535256
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Filing Dt:
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03/23/2000
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Publication #:
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Pub Dt:
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05/16/2002
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Title:
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METHOD FOR FORMING HIGH QUALITY MULTIPLE THICKNESS OXIDE LAYERS BY REDUCING DESCUM INDUCED DEFECTS
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Patent #:
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Issue Dt:
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07/09/2002
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Application #:
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09651684
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Filing Dt:
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08/30/2000
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Title:
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Semiconductor structure
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Patent #:
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Issue Dt:
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10/15/2002
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Application #:
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09723635
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Filing Dt:
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11/28/2000
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Title:
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SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09723653
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Filing Dt:
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11/28/2000
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Title:
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METHOD OF SIMULTANEOUS FORMATION OF BITLINE ISOLATION AND PERIPHEY OXIDE
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Patent #:
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|
Issue Dt:
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09/03/2002
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Application #:
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09772600
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Filing Dt:
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01/30/2001
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Title:
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FLASH MEMORY ERASE SPEED BY FLUORINE IMPLANT OR FLUORINATION
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Patent #:
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Issue Dt:
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08/20/2002
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Application #:
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09893279
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Filing Dt:
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06/27/2001
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Title:
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SOURCE DRAIN IMPLANT DURING ONO FORMATION FOR IMPROVED ISOLATION OF SONOS DEVICES
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Patent #:
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Issue Dt:
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09/28/2004
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Application #:
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10136173
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Filing Dt:
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05/01/2002
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Publication #:
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Pub Dt:
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11/06/2003
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Title:
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SYSTEM AND METHOD FOR MULTI-BIT FLASH READS USING DUAL DYNAMIC REFERENCES
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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10217821
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Filing Dt:
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08/12/2002
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Title:
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SALICIDED GATE FOR VIRTUAL GROUND ARRAYS
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Patent #:
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Issue Dt:
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04/29/2003
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Application #:
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10223195
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Filing Dt:
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08/19/2002
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Publication #:
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Pub Dt:
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12/19/2002
| | | | |
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Title:
|
SIMULTANEOUS FORMATION OF CHARGE STORAGE AND BITLINE TO WORDLINE ISOLATION
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|
|
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Patent #:
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|
Issue Dt:
|
03/16/2004
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Application #:
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10230729
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Filing Dt:
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08/29/2002
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Title:
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DUMMY WORDLINE FOR ERASE AND BITLINE LEAKAGE
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|
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Patent #:
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|
Issue Dt:
|
01/29/2008
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Application #:
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10600065
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Filing Dt:
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06/20/2003
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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MEMORY WITH A CORE-BASED VIRTUAL GROUND AND DYNAMIC REFERENCE SENSING SCHEME
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