Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014770/0236 | |
| Pages: | 13 |
| | Recorded: | 06/24/2004 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
10
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10100485
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Filing Dt:
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03/14/2002
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Publication #:
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Pub Dt:
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01/22/2004
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Title:
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HARD MASK PROCESS FOR MEMORY DEVICE WITHOUT BITLINE SHORTS
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Patent #:
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Issue Dt:
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10/12/2004
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Application #:
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10109234
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Filing Dt:
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03/27/2002
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Title:
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LINER FOR SEMICONDUCTOR MEMORIES AND MANUFACTURING METHOD THEREFOR
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Patent #:
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Issue Dt:
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09/09/2003
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Application #:
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10109235
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Filing Dt:
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03/27/2002
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Title:
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MEMORY WORDLINE HARD MASK
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Patent #:
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Issue Dt:
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11/12/2002
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Application #:
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10109516
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Filing Dt:
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03/27/2002
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Title:
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METHOD OF MAKING MEMORY WORDLINE HARD MASK EXTENSION
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Patent #:
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Issue Dt:
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03/18/2014
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Application #:
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10118732
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Filing Dt:
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04/08/2002
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Publication #:
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Pub Dt:
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10/09/2003
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Title:
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MEMORY MANUFACTURING PROCESS WITH BITLINE ISOLATION
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Patent #:
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Issue Dt:
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04/13/2004
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Application #:
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10126280
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Filing Dt:
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04/19/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING DISPOSABLE ARC FOR WORDLINE FORMATION
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Patent #:
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Issue Dt:
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12/30/2003
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Application #:
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10128771
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Filing Dt:
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04/22/2002
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Title:
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SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10151576
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Filing Dt:
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05/16/2002
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Title:
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MEMORY MANUFACTURING PROCESS USING BITLINE RAPID THERMAL ANNEAL
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Patent #:
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Issue Dt:
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07/11/2006
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Application #:
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10307189
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Filing Dt:
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11/29/2002
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Title:
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MEMORY WITH IMPROVED CHARGE-TRAPPING DIELECTRIC LAYER
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Patent #:
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Issue Dt:
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04/26/2005
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Application #:
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10672093
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Filing Dt:
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09/26/2003
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Title:
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METHOD OF MANUFACTURING A SEMICONDUCTOR MEMORY WITH DEUTERATED MATERIALS
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Assignee
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| ONE AMD PLACE, P.O. BOX 3453 |
| SUNNYVALE, CALIFORNIA 94088-3453 |
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Correspondence name and address
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TAMI TUCKER
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1110 SUNNYVALE-SARATOGA ROAD, SUITE A1
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SUNNYVALE, CA 94087
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