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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:014782/0080   Pages: 21
Recorded: 06/24/2004
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 61
1
Patent #:
6134146
Issue Dt:
10/17/2000
Application #:
09166385
Filing Dt:
10/05/1998
Title:
WORDLINE DRIVER FOR FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY (EEPROM)
2
Patent #:
6147906
Issue Dt:
11/14/2000
Application #:
09419695
Filing Dt:
10/14/1999
Title:
METHOD AND SYSTEM FOR SAVING OVERHEAD PROGRAM TIME IN A MEMORY DEVICE
3
Patent #:
6662262
Issue Dt:
12/09/2003
Application #:
09420535
Filing Dt:
10/19/1999
Title:
OTP SECTOR DOUBLE PROTECTION FOR A SIMULTANEOUS OPERATION FLASH MEMORY
4
Patent #:
6125055
Issue Dt:
09/26/2000
Application #:
09421105
Filing Dt:
10/19/1999
Title:
SECTOR WRITE PROTECT CAMS FOR A SIMULTANEOUS OPERATION FLASH MEMORY
5
Patent #:
6201753
Issue Dt:
03/13/2001
Application #:
09421142
Filing Dt:
10/19/1999
Title:
LATCHING CAM DATA IN A FLASH MEMORY DEVICE
6
Patent #:
6550028
Issue Dt:
04/15/2003
Application #:
09421470
Filing Dt:
10/19/1999
Title:
ARRAY VT MODE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
7
Patent #:
6285585
Issue Dt:
09/04/2001
Application #:
09421471
Filing Dt:
10/19/1999
Title:
OUTPUT SWITCHING IMPLEMENTATION FOR A FLASH MEMORY DEVICE
8
Patent #:
6331950
Issue Dt:
12/18/2001
Application #:
09421757
Filing Dt:
10/19/1999
Title:
WRITE PROTECT INPUT IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
9
Patent #:
6571307
Issue Dt:
05/27/2003
Application #:
09421758
Filing Dt:
10/19/1999
Title:
MULTIPLE PURPOSE BUS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
10
Patent #:
6163478
Issue Dt:
12/19/2000
Application #:
09421774
Filing Dt:
10/19/1999
Title:
COMMON FLASH INTERFACE IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
11
Patent #:
6327181
Issue Dt:
12/04/2001
Application #:
09421775
Filing Dt:
10/19/1999
Title:
REFERENCE CELL BITLINE PATH ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
12
Patent #:
6111787
Issue Dt:
08/29/2000
Application #:
09421776
Filing Dt:
10/19/1999
Title:
ADDRESS TRANSISTION DETECT TIMING ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
13
Patent #:
6185128
Issue Dt:
02/06/2001
Application #:
09421984
Filing Dt:
10/19/1999
Title:
REFERENCE CELL FOUR-WAY SWITCH FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
14
Patent #:
6359808
Issue Dt:
03/19/2002
Application #:
09421985
Filing Dt:
10/19/1999
Title:
LOW VOLTAGE READ CASCODE FOR 2V/3V AND DIFFERENT BANK COMBINATIONS WITHOUT METAL OPTIONS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
15
Patent #:
6259633
Issue Dt:
07/10/2001
Application #:
09422198
Filing Dt:
10/19/1999
Title:
SENSE AMPLIFIER ARCHITECTURE FOR SLIDING BANKS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
16
Patent #:
6118698
Issue Dt:
09/12/2000
Application #:
09422199
Filing Dt:
10/19/1999
Title:
OUTPUT MULTIPLEXING IMPLEMENTATION FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE
17
Patent #:
6212108
Issue Dt:
04/03/2001
Application #:
09490340
Filing Dt:
01/24/2000
Title:
Distributed voltage charge circuits to reduce sensing time in a memory device
18
Patent #:
6243316
Issue Dt:
06/05/2001
Application #:
09501159
Filing Dt:
02/09/2000
Title:
Voltage boost reset circuit for a flash memory
19
Patent #:
6215058
Issue Dt:
04/10/2001
Application #:
09501487
Filing Dt:
02/09/2000
Title:
Remote controlled page turner utilizing a plurality ofmovable fingers
20
Patent #:
6240040
Issue Dt:
05/29/2001
Application #:
09526239
Filing Dt:
03/15/2000
Title:
Multiple bank simultaneous operation for a flash memory
21
Patent #:
6208556
Issue Dt:
03/27/2001
Application #:
09547556
Filing Dt:
04/12/2000
Title:
Address transition detect timing architecture for a simultaneous operation flash memory device
22
Patent #:
6201737
Issue Dt:
03/13/2001
Application #:
09558764
Filing Dt:
04/26/2000
Title:
Apparatus and method to characterize the threshold distribution in an nrom virtual ground array
23
Patent #:
6351420
Issue Dt:
02/26/2002
Application #:
09595519
Filing Dt:
06/16/2000
Title:
Voltage boost level clamping circuit for a flash memory
24
Patent #:
6397313
Issue Dt:
05/28/2002
Application #:
09632390
Filing Dt:
08/04/2000
Title:
REDUNDANT DUAL BANK ARCHITECTURE FOR A SIMULTANEOUS OPERATION FLASH MEMORY
25
Patent #:
6229735
Issue Dt:
05/08/2001
Application #:
09638055
Filing Dt:
08/11/2000
Title:
Burst read mode word line boosting
26
Patent #:
6327194
Issue Dt:
12/04/2001
Application #:
09644358
Filing Dt:
08/23/2000
Title:
Precise reference wordline loading compensation for a high density flash memory device
27
Patent #:
6275412
Issue Dt:
08/14/2001
Application #:
09650401
Filing Dt:
08/29/2000
Title:
Common flash interface implementation for a simultaneous operation flash memory device
28
Patent #:
6298007
Issue Dt:
10/02/2001
Application #:
09652742
Filing Dt:
08/31/2000
Title:
Method and apparatus for eliminating false data in a page mode memory device
29
Patent #:
6266284
Issue Dt:
07/24/2001
Application #:
09661356
Filing Dt:
09/14/2000
Title:
Output buffer for external voltage
30
Patent #:
6275421
Issue Dt:
08/14/2001
Application #:
09661358
Filing Dt:
09/14/2000
Title:
Chip enable input buffer
31
Patent #:
6353566
Issue Dt:
03/05/2002
Application #:
09663552
Filing Dt:
09/18/2000
Title:
System and method for tracking sensing speed by an equalization pulse for a high density flash memory device
32
Patent #:
6463516
Issue Dt:
10/08/2002
Application #:
09663765
Filing Dt:
09/18/2000
Title:
VARIABLE SECTOR SIZE FOR A HIGH DENSITY FLASH MEMORY DEVICE
33
Patent #:
6285627
Issue Dt:
09/04/2001
Application #:
09663909
Filing Dt:
09/18/2000
Title:
Address transition detector architecture for a high density flash memory device
34
Patent #:
6324108
Issue Dt:
11/27/2001
Application #:
09667891
Filing Dt:
09/22/2000
Title:
Application of external voltage during array VT testing
35
Patent #:
6438041
Issue Dt:
08/20/2002
Application #:
09668100
Filing Dt:
09/22/2000
Title:
NEGATIVE VOLTAGE REGULATION
36
Patent #:
6400633
Issue Dt:
06/04/2002
Application #:
09675372
Filing Dt:
09/29/2000
Title:
POWER-SAVING MODES FOR MEMORIES
37
Patent #:
6813735
Issue Dt:
11/02/2004
Application #:
09676623
Filing Dt:
10/02/2000
Title:
I/O BASED COLUMN REDUNDANCY FOR VIRTUAL GROUND WITH 2-BIT CELL FLASH MEMORY
38
Patent #:
6310805
Issue Dt:
10/30/2001
Application #:
09676902
Filing Dt:
10/02/2000
Title:
Architecture for a dual-bank page mode memory with redundancy
39
Patent #:
6400638
Issue Dt:
06/04/2002
Application #:
09680344
Filing Dt:
10/05/2000
Title:
Wordline driver for flash memory read mode
40
Patent #:
6583479
Issue Dt:
06/24/2003
Application #:
09688936
Filing Dt:
10/16/2000
Title:
SIDEWALL NROM AND METHOD OF MANUFACTURE THEREOF FOR NON-VOLATILE MEMORY CELLS
41
Patent #:
6373742
Issue Dt:
04/16/2002
Application #:
09689036
Filing Dt:
10/12/2000
Title:
Two side decoding of a memory array
42
Patent #:
6347052
Issue Dt:
02/12/2002
Application #:
09690554
Filing Dt:
10/17/2000
Title:
Word line decoding architecture in a flash memory
43
Patent #:
6537866
Issue Dt:
03/25/2003
Application #:
09691643
Filing Dt:
10/18/2000
Title:
METHOD OF FORMING NARROW INSULATING SPACERS FOR USE IN REDUCING MINIMUM COMPONENT SIZE
44
Patent #:
6507527
Issue Dt:
01/14/2003
Application #:
09698614
Filing Dt:
10/27/2000
Title:
MEMORY LINE DISCHARGE BEFORE SENSING
45
Patent #:
6297993
Issue Dt:
10/02/2001
Application #:
09712382
Filing Dt:
11/13/2000
Title:
Acceleration voltage implementation for a high density flash memory device
46
Patent #:
6307787
Issue Dt:
10/23/2001
Application #:
09724669
Filing Dt:
11/28/2000
Title:
Burst read incorporating output based redundancy
47
Patent #:
6463003
Issue Dt:
10/08/2002
Application #:
09729388
Filing Dt:
12/04/2000
Publication #:
US20010050874
Pub Dt:
12/13/2001
Title:
POWER SAVING SCHEME FOR BURST MODE IMPLEMENTATION DURING READING OF DATA FROM A MEMORY DEVICE
48
Patent #:
6662003
Issue Dt:
12/09/2003
Application #:
09734844
Filing Dt:
12/11/2000
Publication #:
US20010031629
Pub Dt:
10/18/2001
Title:
SUPERHETERODYNE RECEIVER
49
Patent #:
6528390
Issue Dt:
03/04/2003
Application #:
09798667
Filing Dt:
03/02/2001
Publication #:
US20020132446
Pub Dt:
09/19/2002
Title:
PROCESS FOR FABRICATING A NON-VOLATILE MEMORY DEVICE
50
Patent #:
6713809
Issue Dt:
03/30/2004
Application #:
09809969
Filing Dt:
03/16/2001
Title:
DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
51
Patent #:
6573140
Issue Dt:
06/03/2003
Application #:
09810155
Filing Dt:
03/16/2001
Title:
PROCESS FOR MAKING A DUAL BIT MEMORY DEVICE WITH ISOLATED POLYSILICON FLOATING GATES
52
Patent #:
6621761
Issue Dt:
09/16/2003
Application #:
09829518
Filing Dt:
04/09/2001
Publication #:
US20020012278
Pub Dt:
01/31/2002
Title:
BURST ARCHITECTURE FOR A FLASH MEMORY
53
Patent #:
6611473
Issue Dt:
08/26/2003
Application #:
10061620
Filing Dt:
02/01/2002
Publication #:
US20020071331
Pub Dt:
06/13/2002
Title:
POWER-SAVING MODES FOR MEMORIES
54
Patent #:
6750103
Issue Dt:
06/15/2004
Application #:
10086112
Filing Dt:
02/27/2002
Title:
NROM CELL WITH N-LESS CHANNEL
55
Patent #:
7142454
Issue Dt:
11/28/2006
Application #:
10243315
Filing Dt:
09/12/2002
Publication #:
US20040052111
Pub Dt:
03/18/2004
Title:
SYSTEM AND METHOD FOR Y-DECODING IN A FLASH MEMORY DEVICE
56
Patent #:
6728160
Issue Dt:
04/27/2004
Application #:
10243433
Filing Dt:
09/12/2002
Title:
PATH GATE DRIVER CIRCUIT
57
Patent #:
6744666
Issue Dt:
06/01/2004
Application #:
10243792
Filing Dt:
09/12/2002
Title:
METHOD AND SYSTEM TO MINIMIZE PAGE PROGRAMMING TIME FOR FLASH MEMORY DEVICES
58
Patent #:
6859393
Issue Dt:
02/22/2005
Application #:
10264387
Filing Dt:
10/04/2002
Title:
GROUND STRUCTURE FOR PAGE READ AND PAGE WRITE FOR FLASH MEMORY
59
Patent #:
6936515
Issue Dt:
08/30/2005
Application #:
10387774
Filing Dt:
03/12/2003
Title:
MEMORY DEVICE HAVING REVERSE LDD
60
Patent #:
6944057
Issue Dt:
09/13/2005
Application #:
10431065
Filing Dt:
05/06/2003
Title:
METHOD TO OBTAIN TEMPERATURE INDEPENDENT PROGRAM THRESHOLD VOLTAGE DISTRIBUTION USING TEMPERATURE DEPENDENT VOLTAGE REFERENCE
61
Patent #:
6791880
Issue Dt:
09/14/2004
Application #:
10431320
Filing Dt:
05/06/2003
Title:
NON-VOLATILE MEMORY READ CIRCUIT WITH END OF LIFE SIMULATION
Assignor
1
ADVANCED MICRO DEVICES, INC.
Exec Dt:
05/15/2004
Assignee
1
AMD (U.S.) HOLDINGS, INC.
ONE AMD PLACE
P.O. BOX 3453
SUNNYVALE, CALIFORNIA 94088-3453
Correspondence name and address
WAGNER, MURABITO & HAO LLP
2 N. MARKET STREET
THIRD FLOOR
SAN JOSE, CA 95113

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