Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014805/0456 | |
| Pages: | 6 |
| | Recorded: | 07/01/2004 | | |
| Conveyance: | CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY PREVIOUSLY RECORDED ON REEL 014066 FRAME 0082. |
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Total properties:
5
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Patent #:
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Issue Dt:
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07/09/1991
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Application #:
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07354268
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Filing Dt:
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05/19/1989
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Title:
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CAD DRIVEN MICROPROBE INTEGRATED CIRCUIT TESTER
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Patent #:
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Issue Dt:
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05/28/1991
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Application #:
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07527661
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Filing Dt:
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05/21/1990
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Title:
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CONTACT SENSING FOR INTEGRATED CIRCUIT TESTING
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Patent #:
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Issue Dt:
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11/24/1992
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Application #:
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07644231
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Filing Dt:
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01/22/1991
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Title:
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PROGRAMMABLE ANTIFUSE STRUCTURE, PROCESS, LOGIC CELL AND ARCHITECTURE FOR PROGRAMMABLE INTEGRATED CIRCUITS
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Patent #:
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Issue Dt:
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07/11/2000
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Application #:
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08994996
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Filing Dt:
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12/19/1997
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Title:
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A METHOD OF AUTOMATING THE MANIPULATION AND DISPLAY OF SETS OF WAFER YIELD DATA USING A USER INTERFACE SMART MACRO.
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Patent #:
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Issue Dt:
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02/06/2001
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Application #:
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09192164
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Filing Dt:
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11/13/1998
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Title:
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IC TEST SOFTWARE SYSTEM FOR MAPPING LOGICAL FUNCTIONAL TEST DATA OF LOGIC INTEGRATED CIRCUITS TO PHYSICAL REPRESENTATION
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Assignee
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| 5350 NE DAWSON CREEK DRIVE |
| HILLSBORO, OREGON 97124-5793 |
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Correspondence name and address
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MICHAEL O. SCHEINBERG
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P.O. BOX 164140
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AUSTIN, TX 78746-4140
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