Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 014945/0041 | |
| Pages: | 3 |
| | Recorded: | 02/02/2004 | | |
| Conveyance: | RE-RECORD TO CORRECT THE ASSIGNEE ON A PREVIOUS RECORDING ON JUNE 26, 2003 AT REEL 014265 FRAME 0144 (ASSIGNMENT) |
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Total properties:
1
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Patent #:
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NONE
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Issue Dt:
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Application #:
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10606225
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Filing Dt:
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06/26/2003
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Publication #:
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Pub Dt:
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02/12/2004
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Title:
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Clock multiplying PLL circuit
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Assignee
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| 1-1, KAMIKODANAKA 4-CHOME, MAKAHARA-KU |
| KAWASAKI-SHI |
| KANAGAWA 211-8588, JAPAN |
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Correspondence name and address
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ARENT FOX KINTNER PLOTKIN ET AL.
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CHARLES M. MARMELSTEIN
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1050 CONNECTICUT AVENUE, N.W., SUITE 400
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ASHINGTON, DC 20036-5339
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