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Patent Assignment Details
NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:015242/0574   Pages: 36
Recorded: 10/13/2004
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 113
Page 2 of 2
Pages: 1 2
1
Patent #:
Issue Dt:
02/18/2003
Application #:
10132051
Filing Dt:
04/24/2002
Publication #:
Pub Dt:
08/22/2002
Title:
TEST SYSTEM HAVING INTERFACE MODULE
2
Patent #:
Issue Dt:
02/08/2005
Application #:
10136710
Filing Dt:
04/30/2002
Publication #:
Pub Dt:
01/23/2003
Title:
OPEN-LOOP FOR WAVEFORM ACQUISITION
3
Patent #:
Issue Dt:
01/25/2005
Application #:
10159527
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/26/2002
Title:
SUB-RESOLUTION ALIGNMENT OF IMAGES
4
Patent #:
Issue Dt:
02/15/2005
Application #:
10160606
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/04/2003
Title:
METHOD AND APPARATUS FOR FORMING A CAVITY IN A SEMICONDUCTOR SUBSTRATE USING A CHARGED PARTICLE BEAM
5
Patent #:
Issue Dt:
10/18/2005
Application #:
10161272
Filing Dt:
05/30/2002
Publication #:
Pub Dt:
12/04/2003
Title:
METHOD FOR DETERMINING THICKNESS OF A SEMICONDUCTOR SUBSTRATE AT THE FLOOR OF A TRENCH
6
Patent #:
Issue Dt:
06/01/2004
Application #:
10197134
Filing Dt:
07/16/2002
Publication #:
Pub Dt:
01/22/2004
Title:
TEST SYSTEM AND METHODOLOGY
7
Patent #:
Issue Dt:
06/14/2005
Application #:
10288896
Filing Dt:
11/06/2002
Publication #:
Pub Dt:
07/17/2003
Title:
PRECISE, IN-SITU ENDPOINT DETECTION FOR CHARGED PARTICLE BEAM PROCESSING
8
Patent #:
NONE
Issue Dt:
Application #:
10371353
Filing Dt:
02/18/2003
Publication #:
Pub Dt:
08/21/2003
Title:
Signal paths providing multiple test configurations
9
Patent #:
Issue Dt:
08/24/2004
Application #:
10382343
Filing Dt:
03/04/2003
Publication #:
Pub Dt:
09/09/2004
Title:
METHOD AND APPARATUS FOR ACCESSING INTERNAL NODES OF AN INTEGRATED CIRCUIT USING IC PACKAGE SUBSTRATE
10
Patent #:
NONE
Issue Dt:
Application #:
10420675
Filing Dt:
04/21/2003
Publication #:
Pub Dt:
05/06/2004
Title:
Method for surface preparation to enable uniform etching of polycrystalline materials
11
Patent #:
NONE
Issue Dt:
Application #:
10421059
Filing Dt:
04/23/2003
Publication #:
Pub Dt:
01/22/2004
Title:
Method for backside die thinning and polishing of packaged integrated circuits
12
Patent #:
Issue Dt:
12/27/2005
Application #:
10466366
Filing Dt:
12/08/2003
Publication #:
Pub Dt:
05/06/2004
Title:
POWER SUPPLY DEVICE FOR A COMPONENT TESTING INSTALLATION
13
Patent #:
Issue Dt:
06/13/2006
Application #:
10678438
Filing Dt:
10/03/2003
Publication #:
Pub Dt:
04/07/2005
Title:
FIB MILLING OF COPPER OVER ORGANIC DIELECTRICS
Assignor
1
Exec Dt:
07/13/2004
Assignee
1
1421 CALIFORNIA CIRCLE
MILPITAS, CALIFORNIA 95035
Correspondence name and address
DORSEY & WHITNEY LLP
GREGORY P. DURBIN
370 SEVENTEENTH STREET
SUITE 4700
DENVER, CO 80202-5647

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