Patent Assignment Details
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For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 015270/0843 | |
| Pages: | 3 |
| | Recorded: | 10/20/2004 | | |
| Attorney Dkt #: | INFN/WB0079 |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
1
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Patent #:
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Issue Dt:
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01/10/2006
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Application #:
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10831466
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Filing Dt:
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04/23/2004
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Publication #:
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Pub Dt:
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12/09/2004
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Title:
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INTEGRATED MEMORY CIRCUIT HAVING A REDUNDANCY CIRCUIT AND A METHOD FOR REPLACING A MEMORY AREA
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Assignee
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| ST.-MARTIN-STR. 53 |
| MUNICH, GERMANY 81669 |
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Correspondence name and address
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MOSER, PATTERSON & SHERIDAN, LLP
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INFINEON
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3040 POST OAK BLVD.,
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SUITE 1500
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HOUSTON, TX 77056
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